Datasheet
Table Of Contents
- Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
- Introduction
- DC Characteristics
- Power-On/Off Power Supply Sequencing
- DC Input and Output Levels
- AC Switching Characteristics
- Performance Characteristics
- IOB Pad Input/Output/3-State
- I/O Standard Adjustment Measurement Methodology
- Input/Output Logic Switching Characteristics
- Input Serializer/Deserializer Switching Characteristics
- Output Serializer/Deserializer Switching Characteristics
- Input/Output Delay Switching Characteristics
- CLB Switching Characteristics
- CLB Distributed RAM Switching Characteristics (SLICEM Only)
- CLB Shift Register Switching Characteristics (SLICEM Only)
- Block RAM and FIFO Switching Characteristics
- DSP48E1 Switching Characteristics
- Clock Buffers and Networks
- MMCM Switching Characteristics
- PLL Switching Characteristics
- Device Pin-to-Pin Output Parameter Guidelines
- Device Pin-to-Pin Input Parameter Guidelines
- Additional Package Parameter Guidelines
- XADC Specifications
- Configuration Switching Characteristics
- eFUSE Programming Conditions
- References
- Revision History
- Please Read: Important Legal Notices
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 16
Table 17: IOB High Range (HR) Switching Characteristics
I/O Standard
T
IOPI
T
IOOP
T
IOTP
Units
V
CCINT
Operating Voltage and Speed Grade
1.0V 0.95V 1.0V 0.95V 1.0V 0.95V
-2 -1 -1L -2 -1 -1L -2 -1 -1L
LVTTL_S4 1.34 1.41 1.41 3.93 4.18 4.18 3.96 4.20 4.20 ns
LVTTL_S8 1.34 1.41 1.41 3.66 3.92 3.92 3.69 3.93 3.93 ns
LVTTL_S12 1.341.411.413.653.903.903.683.913.91ns
LVTTL_S16 1.341.411.413.193.453.453.223.463.46ns
LVTTL_S24 1.341.411.413.413.673.673.443.683.68ns
LVTTL_F4 1.34 1.41 1.41 3.38 3.64 3.64 3.41 3.65 3.65 ns
LVTTL_F8 1.34 1.41 1.41 2.87 3.12 3.12 2.90 3.13 3.13 ns
LVTTL_F12 1.341.411.412.853.103.102.883.123.12ns
LVTTL_F16 1.341.411.412.682.932.932.712.952.95ns
LVTTL_F24 1.341.411.412.652.902.902.682.912.91ns
LVDS_25 0.810.880.881.411.671.671.441.681.68ns
MINI_LVDS_25 0.81 0.88 0.88 1.40 1.65 1.65 1.43 1.66 1.66 ns
BLVDS_25 0.81 0.88 0.88 1.96 2.21 2.21 1.99 2.23 2.23 ns
RSDS_25 (point to point) 0.81 0.88 0.88 1.40 1.65 1.65 1.43 1.66 1.66 ns
PPDS_25 0.810.880.881.411.671.671.441.681.68ns
TMDS_33 0.810.880.881.541.791.791.571.801.80ns
PCI33_3 1.321.391.393.223.483.483.253.493.49ns
HSUL_12_S 0.750.820.821.932.182.181.962.202.20ns
HSUL_12_F 0.750.820.821.411.671.671.441.681.68ns
DIFF_HSUL_12_S 0.76 0.83 0.83 1.93 2.18 2.18 1.96 2.20 2.20 ns
DIFF_HSUL_12_F 0.76 0.83 0.83 1.41 1.67 1.67 1.44 1.68 1.68 ns
MOBILE_DDR_S 0.84 0.91 0.91 1.80 2.06 2.06 1.83 2.07 2.07 ns
MOBILE_DDR_F 0.84 0.91 0.91 1.51 1.76 1.76 1.54 1.77 1.77 ns
DIFF_MOBILE_DDR_S 0.78 0.85 0.85 1.82 2.07 2.07 1.85 2.09 2.09 ns
DIFF_MOBILE_DDR_F 0.78 0.85 0.85 1.57 1.82 1.82 1.60 1.84 1.84 ns
HSTL_I_S 0.75 0.82 0.82 1.74 1.99 1.99 1.77 2.01 2.01 ns
HSTL_II_S 0.730.800.801.541.791.791.571.801.80ns
HSTL_I_18_S 0.750.820.821.411.671.671.441.681.68ns
HSTL_II_18_S 0.75 0.81 0.81 1.54 1.79 1.79 1.57 1.80 1.80 ns
DIFF_HSTL_I_S 0.76 0.83 0.83 1.71 1.96 1.96 1.74 1.98 1.98 ns
DIFF_HSTL_II_S 0.760.830.831.631.881.881.661.901.90ns
DIFF_HSTL_I_18_S 0.790.860.861.511.761.761.541.771.77ns
DIFF_HSTL_II_18_S 0.78 0.85 0.85 1.58 1.84 1.84 1.61 1.85 1.85 ns
HSTL_I_F 0.75 0.82 0.82 1.22 1.48 1.48 1.25 1.49 1.49 ns
HSTL_II_F 0.730.800.801.241.491.491.271.511.51ns
HSTL_I_18_F 0.750.820.821.261.511.511.291.521.52ns
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