Datasheet
Table Of Contents
- Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
- Introduction
- DC Characteristics
- Power-On/Off Power Supply Sequencing
- DC Input and Output Levels
- AC Switching Characteristics
- Performance Characteristics
- IOB Pad Input/Output/3-State
- I/O Standard Adjustment Measurement Methodology
- Input/Output Logic Switching Characteristics
- Input Serializer/Deserializer Switching Characteristics
- Output Serializer/Deserializer Switching Characteristics
- Input/Output Delay Switching Characteristics
- CLB Switching Characteristics
- CLB Distributed RAM Switching Characteristics (SLICEM Only)
- CLB Shift Register Switching Characteristics (SLICEM Only)
- Block RAM and FIFO Switching Characteristics
- DSP48E1 Switching Characteristics
- Clock Buffers and Networks
- MMCM Switching Characteristics
- PLL Switching Characteristics
- Device Pin-to-Pin Output Parameter Guidelines
- Device Pin-to-Pin Input Parameter Guidelines
- Additional Package Parameter Guidelines
- XADC Specifications
- Configuration Switching Characteristics
- eFUSE Programming Conditions
- References
- Revision History
- Please Read: Important Legal Notices
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 15
IOB Pad Input/Output/3-State
Table 17 summarizes the values of standard-specific data input delay adjustments, output delays
terminating at pads (based on standard) and 3-state delays.
• T
IOPI
is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The
delay varies depending on the capability of the SelectIO input buffer.
• T
IOOP
is described as the delay from the O pin to the IOB pad through the output buffer of an IOB
pad. The delay varies depending on the capability of the SelectIO output buffer.
• T
IOTP
is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad,
when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer.
In HR I/O banks, the IN_TERM termination turn-on time is always faster than T
IOTP
when the
INTERMDISABLE pin is used.
DDR LVDS receiver
(1)
1250 950 950 Mb/s
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
Table 16: Maximum Physical Interface (PHY) Rate for Memory Interface IP available with the Memory Interface
Generator
(1)
Memory Standard
V
CCINT
Operating Voltage, Speed Grade,
and Temperature Range
Units
1.0V 0.95V
-2C/-2I -1C/-1I/-1Q -1LI
4:1 Memory Controllers
DDR3 800
(2)
667 667 Mb/s
DDR3L 800
(2)
667 667 Mb/s
DDR2 800
(2)
667 667 Mb/s
2:1 Memory Controllers
DDR3 800
(2)
667 667 Mb/s
DDR3L 800
(2)
667 667 Mb/s
DDR2 800
(2)
667 667 Mb/s
LPDDR2 667 533 533 Mb/s
Notes:
1. V
REF
tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586)
[Ref 7].
2. The maximum PHY rate is 667 Mb/s in the FTGB196 package.
Table 15: Networking Applications Interface Performances (Cont’d)
Description
V
CCINT
Operating Voltage, Speed
Grade, and Temperature Range
Units
1.0V 0.95V
-2C/-2I -1C/-1I/-1Q -1LI
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