Datasheet
Table Of Contents
- Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
- Introduction
- DC Characteristics
- Power-On/Off Power Supply Sequencing
- DC Input and Output Levels
- AC Switching Characteristics
- Performance Characteristics
- IOB Pad Input/Output/3-State
- I/O Standard Adjustment Measurement Methodology
- Input/Output Logic Switching Characteristics
- Input Serializer/Deserializer Switching Characteristics
- Output Serializer/Deserializer Switching Characteristics
- Input/Output Delay Switching Characteristics
- CLB Switching Characteristics
- CLB Distributed RAM Switching Characteristics (SLICEM Only)
- CLB Shift Register Switching Characteristics (SLICEM Only)
- Block RAM and FIFO Switching Characteristics
- DSP48E1 Switching Characteristics
- Clock Buffers and Networks
- MMCM Switching Characteristics
- PLL Switching Characteristics
- Device Pin-to-Pin Output Parameter Guidelines
- Device Pin-to-Pin Input Parameter Guidelines
- Additional Package Parameter Guidelines
- XADC Specifications
- Configuration Switching Characteristics
- eFUSE Programming Conditions
- References
- Revision History
- Please Read: Important Legal Notices
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 11
LVDS DC Specifications (LVDS_25)
Table 11: LVDS_25 DC Specifications
(1)
Symbol DC Parameter Conditions Min Typ Max Units
V
CCO
Supply voltage. 2.375 2.500 2.625 V
V
OH
Output High voltage for Q and Q.R
T
=100Ω across Q and Q signals. – – 1.675 V
V
OL
Output Low voltage for Q and Q.R
T
=100Ω across Q and Q signals. 0.700 – – V
V
ODIFF
Differential output voltage:
(Q – Q
), Q = High
(Q
– Q), Q =High
R
T
=100Ω across Q and Q signals. 247 350 600 mV
V
OCM
Output common-mode voltage. R
T
= 100Ω across Q and Q signals. 1.000 1.250 1.425 V
V
IDIFF
Differential input voltage:
(Q – Q
), Q = High
(Q
– Q), Q =High
100 350 600 mV
V
ICM
Input common-mode voltage. 0.300 1.200 1.500 V
Notes:
1. Differential inputs for LVDS_25 can be placed in banks with V
CCO
levels that are different from the required level for outputs. Consult the
7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3] for more information.
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