Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.9) March 13, 2019 Product Specification Introduction Spartan®-7 FPGAs are available in -2, -1, and -1L speed grades, with -2 having the highest performance. The Spartan-7 FPGAs predominantly operate at a 1.0V core voltage. The -1L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 devices. The -1L devices operate only at VCCINT = VCCBRAM = 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 1: Absolute Maximum Ratings(1) (Cont’d) Symbol Description Min Max Units I/O input voltage. –0.4 VCCO + 0.55 V VIN(2)(3)(4) I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33.(5) –0.4 2.625 V VCCBATT Key memory battery backup supply. –0.5 2.0 V VCCADC XADC supply relative to GNDADC. –0.5 2.0 V VREFP XADC reference input relative to GNDADC. –0.5 2.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 2: Recommended Operating Conditions(1)(2) Symbol Description Min Typ Max Units For -2 and -1 (1.0V) devices: internal supply voltage. 0.95 1.00 1.05 V For -1L (0.95V) devices: internal supply voltage. 0.92 0.95 0.98 V Auxiliary supply voltage. 1.71 1.80 1.89 V For -2 and -1 (1.0V) devices: block RAM supply voltage. 0.95 1.00 1.05 V For -1L (0.95V) devices: block RAM supply voltage. 0.92 0.95 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ(1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost). 0.75 – – V VDRI Data retention VCCAUX voltage (below which configuration data might be lost). 1.5 – – V IREF VREF leakage current per pin. – – 15 µA IL Input or output leakage current per pin (sample-tested).
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2) AC Voltage Overshoot % of UI at –40°C to 125°C VCCO + 0.55 AC Voltage Undershoot % of UI at –40°C to 125°C –0.40 100 –0.45 61.7 –0.50 25.8 –0.55 11.0 100 VCCO + 0.60 46.6 –0.60 4.77 VCCO + 0.65 21.2 –0.65 2.10 VCCO + 0.70 9.75 –0.70 0.94 VCCO + 0.75 4.55 –0.75 0.43 VCCO + 0.80 2.15 –0.80 0.20 VCCO + 0.85 1.02 –0.85 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 5: Typical Quiescent Supply Current(1)(2)(3) (Cont’d) Speed Grade Symbol ICCOQ ICCAUXQ Description Quiescent VCCO supply current. Quiescent VCCAUX supply current. DS189 (v1.9) March 13, 2019 Product Specification Device 1.0V 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 5: Typical Quiescent Supply Current(1)(2)(3) (Cont’d) Speed Grade Symbol ICCBRAMQ Description Quiescent VCCBRAM supply current. Device 1.0V 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 6 shows the minimum current, in addition to I CCQ maximum, that is required by Spartan-7 devices for proper power-on and configuration. If the current minimums shown in Table 6 are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and V OH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum V CCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 9: Differential SelectIO DC Input and Output Levels VICM(1) I/O Standard V, Typ V, Max V, Min VOCM(3) VOD(4) V, Typ V, Max V, Min V, Typ V, Max – – – 1.250 – Note 5 MINI_LVDS_25 0.300 1.200 VCCAUX 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600 PPDS_25 0.200 0.900 VCCAUX 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400 RSDS_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics LVDS DC Specifications (LVDS_25) Table 11: LVDS_25 DC Specifications(1) Symbol DC Parameter Conditions Min Typ Max Units 2.375 2.500 2.625 V VCCO Supply voltage. VOH Output High voltage for Q and Q. RT = 100Ω across Q and Q signals. – – 1.675 V VOL Output Low voltage for Q and Q. RT = 100Ω across Q and Q signals. 0.700 – – V RT = 100Ω across Q and Q signals. 247 350 600 mV RT = 100Ω across Q and Q signals. 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics AC Switching Characteristics All values represented in this data sheet are based on the speed specifications from the Vivado® Design Suite as outlined in Table 12. Table 12: Speed Specification Version By Device 2018.2.1 Device 1.23 XC7S6, XC7S15, XC7S25, XC7S50, XC7S75, XC7S100 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Speed Grade Designations Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Spartan-7 device on a per speed grade basis.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 14: Spartan-7 Device Production Software and Speed Specification Release VCCINT Operating Voltage, Speed Grade, and Temperature Range 1.0V Device -2C -2I 0.95V -1C -1I -1Q -1LI XC7S6 Vivado tools 2018.2 v1.22 Vivado tools 2018.2.1 v1.23 Vivado tools 2018.2 v1.22 XC7S15 Vivado tools 2018.2 v1.22 Vivado tools 2018.2.1 v1.23 Vivado tools 2018.2 v1.22 XC7S25 Vivado tools 2017.4 v1.20 Vivado tools 2018.1 v1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 15: Networking Applications Interface Performances (Cont’d) VCCINT Operating Voltage, Speed Grade, and Temperature Range Description 1.0V DDR LVDS receiver(1) 0.95V -2C/-2I -1C/-1I/-1Q -1LI 1250 950 950 Units Mb/s Notes: 1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 17: IOB High Range (HR) Switching Characteristics TIOOP TIOPI TIOTP VCCINT Operating Voltage and Speed Grade I/O Standard 1.0V 0.95V 1.0V 0.95V 1.0V 0.95V Units -2 -1 -1L -2 -1 -1L -2 -1 -1L LVTTL_S4 1.34 1.41 1.41 3.93 4.18 4.18 3.96 4.20 4.20 ns LVTTL_S8 1.34 1.41 1.41 3.66 3.92 3.92 3.69 3.93 3.93 ns LVTTL_S12 1.34 1.41 1.41 3.65 3.90 3.90 3.68 3.91 3.91 ns LVTTL_S16 1.34 1.41 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) TIOPI TIOOP TIOTP VCCINT Operating Voltage and Speed Grade I/O Standard 1.0V 0.95V 1.0V 0.95V 1.0V 0.95V Units -2 -1 -1L -2 -1 -1L -2 -1 -1L HSTL_II_18_F 0.75 0.81 0.81 1.24 1.49 1.49 1.27 1.51 1.51 ns DIFF_HSTL_I_F 0.76 0.83 0.83 1.30 1.56 1.56 1.33 1.57 1.57 ns DIFF_HSTL_II_F 0.76 0.83 0.83 1.33 1.59 1.59 1.36 1.60 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) TIOPI TIOOP TIOTP VCCINT Operating Voltage and Speed Grade I/O Standard 1.0V 0.95V 1.0V 0.95V 1.0V 0.95V Units -2 -1 -1L -2 -1 -1L -2 -1 -1L LVCMOS15_F8 0.86 0.93 0.93 1.72 1.98 1.98 1.75 1.99 1.99 ns LVCMOS15_F12 0.86 0.93 0.93 1.47 1.73 1.73 1.50 1.74 1.74 ns LVCMOS15_F16 0.86 0.93 0.93 1.46 1.71 1.71 1.49 1.73 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 18: IOB 3-state Output Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units TIOTPHZ T input to pad high-impedance. 2.19 2.37 2.37 ns TIOIBUFDISABLE IBUF turn-on time from IBUFDISABLE to O output. 2.30 2.60 2.60 ns DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 19 shows the test setup parameters used for measuring input delay. Table 19: Input Delay Measurement Methodology Description I/O Standard Attribute VL(1) VH(1) VMEAS(3)(5) VREF(2)(4) LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 – LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75 – LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9 – LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 19: Input Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute VL(1) VH(1) VMEAS(3)(5) VREF(2)(4) PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0(5) – RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0(5) – TMDS_33 TMDS_33 3 – 0.125 3 + 0.125 0(5) – Notes: 1. 2. 3. 4. 5. Input waveform switches between VL and VH. Measurements are made at typical, minimum, and maximum VREF values.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Output Delay Measurements Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 1 and Figure 2.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 20: Output Delay Measurement Methodology Description I/O Standard Attribute RREF (Ω) CREF(1) VMEAS (pF) (V) VREF (V) LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0 LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0 LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0 LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0 LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0 LVTTL, 3.3V LVTTL 1M 0 1.65 0 PCI33, 3.3V PCI33_3 25 10 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input/Output Logic Switching Characteristics Table 21: ILOGIC Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V -2 0.95V -1 Units -1L Setup/Hold TICE1CK/TICKCE1 CE1 pin setup/hold with respect to CLK. 0.54/0.02 0.76/0.02 0.76/0.02 ns TISRCK/TICKSR SR pin setup/hold with respect to CLK. 0.70/0.01 1.13/0.01 1.13/0.01 ns TIDOCK/TIOCKD D pin setup/hold with respect to CLK without delay. 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 22: OLOGIC Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V -2 0.95V -1 Units -1L Setup/Hold TODCK/TOCKD D1/D2 pins setup/hold with respect to CLK. 0.71/–0.11 0.84/–0.11 0.84/–0.11 ns TOOCECK/TOCKOCE OCE pin setup/hold with respect to CLK. 0.34/0.58 0.51/0.58 0.51/0.58 ns TOSRCK/TOCKSR SR pin setup/hold with respect to CLK. 0.44/0.21 0.80/0.21 0.80/0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input Serializer/Deserializer Switching Characteristics Table 23: ISERDES Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L 0.02/0.15 0.02/0.17 0.02/0.17 Units Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin setup/hold with respect to CLKDIV. TISCCK_CE/ TISCKC_CE CE pin setup/hold with respect to CLK (for CE1). 0.50/–0.01 0.72/–0.01 0.72/–0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Output Serializer/Deserializer Switching Characteristics Table 24: OSERDES Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L 0.45/0.03 0.63/0.03 0.63/0.03 Units Setup/Hold TOSDCK_D/ TOSCKD_D D input setup/hold with respect to CLKDIV. TOSDCK_T/ TOSCKD_T T input setup/hold with respect to CLK. 0.73/–0.13 0.88/–0.13 0.88/–0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input/Output Delay Switching Characteristics Table 25: Input/Output Delay Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units IDELAYCTRL TDLYCCO_RDY FIDELAYCTRL_REF Reset to ready for IDELAYCTRL. 3.67 3.67 3.67 µs Attribute REFCLK frequency = 200.00.(1) 200.00 200.00 200.00 MHz Attribute REFCLK frequency = 300.00.(1) 300.00 300.00 300.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 26: IO_FIFO Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units IO_FIFO Clock to Out Delays TOFFCKO_DO RDCLK to Q outputs. 0.60 0.68 0.68 ns TCKO_FLAGS Clock to IO_FIFO flags. 0.61 0.77 0.77 ns 0.51/0.02 0.58/0.02 0.58/0.02 ns Setup/Hold TCCK_D/TCKC_D D inputs to WRCLK. TIFFCCK_WREN/ TIFFCKC_WREN WREN to WRCLK.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics CLB Switching Characteristics Table 27: CLB Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units Combinatorial Delays TILO An – Dn LUT address to A. 0.11 0.13 0.13 ns, Max TILO_2 An – Dn LUT address to AMUX/CMUX. 0.30 0.36 0.36 ns, Max TILO_3 An – Dn LUT address to BMUX_A. 0.46 0.55 0.55 ns, Max TITO An – Dn inputs to A – D Q outputs. 1.05 1.27 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 28: CLB Distributed RAM Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units Sequential Delays TSHCKO Clock to A – B outputs. 1.09 1.32 1.32 ns, Max TSHCKO_1 Clock to AMUX – BMUX outputs. 1.53 1.86 1.86 ns, Max Setup and Hold Times Before/After Clock CLK TDS_LRAM/TDH_LRAM A – D inputs to CLK. 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Block RAM and FIFO Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V Units -2 -1 -1L Clock CLK to DOUT output (without output register).(1)(2) 2.13 2.46 2.46 ns, Max Clock CLK to DOUT output (with output register).(3)(4) 0.74 0.89 0.89 ns, Max Clock CLK to DOUT output with ECC (without output register).(1)(2) 3.04 3.84 3.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics (Cont’d) VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units TRDCK_DI_ECC_FIFO/ TRCKD_DI_ECC_FIFO DIN inputs with FIFO ECC in standard mode.(8) 1.15/0.59 1.32/0.64 1.32/0.64 ns, Min TRCCK_INJECTBITERR/ TRCKC_INJECTBITERR Inject single/double bit error in ECC mode. 0.64/0.37 0.74/0.40 0.74/0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics (Cont’d) VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V Units -2 -1 -1L When in cascade RF mode and there is a possibility of address overlap between port A and port B. 362.19 297.35 297.35 MHz FMAX_FIFO FIFO in all modes without ECC. 460.83 388.20 388.20 MHz FMAX_ECC Block RAM and FIFO in ECC configuration. 365.10 297.53 297.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DSP48E1 Switching Characteristics Table 31: DSP48E1 Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade 1.0V Units 0.95V -2 -1 -1L Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_AREG/ TDSPCKD_A_AREG A input to A register CLK. 0.30/ 0.13 0.37/ 0.14 0.37/ 0.14 ns TDSPDCK_B_BREG/ TDSPCKD_B_BREG B input to B register CLK. 0.38/ 0.16 0.45/ 0.18 0.45/ 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 31: DSP48E1 Switching Characteristics (Cont’d) Symbol Description VCCINT Operating Voltage and Speed Grade 1.0V Units 0.95V -2 -1 -1L TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG CEM input to M register CLK. 0.21/ 0.20 0.27/ 0.23 0.27/ 0.23 ns TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG CEP input to P register CLK. 0.43/ 0.01 0.53/ 0.01 0.53/ 0.01 ns TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ {RSTA, RSTB} input to {A, B} register CLK.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 31: DSP48E1 Switching Characteristics (Cont’d) Symbol Description VCCINT Operating Voltage and Speed Grade 1.0V TDSPDO_PCIN_CARRYCASCOUT PCIN input to CARRYCASCOUT output. Units 0.95V -2 -1 -1L 1.56 1.85 1.85 ns Clock to Outs from Output Register Clock to Output Pins TDSPCKO_P_PREG CLK PREG to P output. 0.37 0.44 0.44 ns TDSPCKO_CARRYCASCOUT_PREG CLK PREG to CARRYCASCOUT output. 0.59 0.69 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Clock Buffers and Networks Table 32: Global Clock Switching Characteristics (Including BUFGCTRL) VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V -2 0.95V -1 Units -1L TBCCCK_CE/TBCCKC_CE(1) CE pins setup/hold. 0.13/0.40 0.16/0.41 0.16/0.41 ns TBCCCK_S/ TBCCKC_S(1) 0.13/0.40 0.16/0.41 0.16/0.41 ns TBCCKO_O (2) S pins setup/hold. BUFGCTRL delay from I0/I1 to O. 0.09 0.10 0.10 ns 628.00 464.00 464.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 35: Horizontal Clock Buffer Switching Characteristics (BUFH) VCCINT Operating Voltage and Speed Grade Symbol TBHCKO_O Description 1.0V Units -2 -1 -1L 0.11 0.13 0.13 ns 0.22/0.15 0.28/0.21 0.28/0.21 ns 628.00 464.00 464.00 MHz BUFH delay from I to O. TBHCCK_CE/ TBHCKC_CE CE pin setup and hold. 0.95V Maximum Frequency FMAX_BUFH Horizontal clock buffer (BUFH).
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics MMCM Switching Characteristics Table 37: MMCM Specification VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units MMCM_FINMAX Maximum input clock frequency. 800.00 800.00 800.00 MHz MMCM_FINMIN Minimum input clock frequency. 10.00 10.00 10.00 MHz MMCM_FINJITTER Maximum input clock period jitter. < 20% of clock input period or 1 ns Max MMCM_FINDUTY Allowable input duty cycle: 10—49 MHz.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 37: MMCM Specification (Cont’d) VCCINT Operating Voltage and Speed Grade Symbol Description TMMCMDCK_PSINCDEC/ TMMCMCKD_PSINCDEC Setup and hold of phase-shift increment/decrement. TMMCMCKO_PSDONE Phase shift clock-to-out of PSDONE. 1.0V 0.95V Units -2 -1 -1L 1.04/0.00 1.04/0.00 1.04/0.00 ns 0.68 0.81 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 38: PLL Specification VCCINT Operating Voltage and Speed Grade Symbol PLL_FBANDWIDTH Description 1.0V -2 -1 -1L Low PLL bandwidth at typical. 1.00 1.00 1.00 MHz High PLL bandwidth at typical.(1) 4.00 4.00 4.00 MHz 0.12 0.12 0.12 ns PLL_TSTATPHAOFFSET Static phase offset of the PLL outputs.(2) PLL_TOUTJITTER Units 0.95V PLL output jitter.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Device Pin-to-Pin Output Parameter Guidelines Table 39: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)(1) VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)(1) VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOFFAR Clock-capable clock input and OUTFF at pins/banks farthest from the BUFGs without MMCM/PLL (far clock region).(2) XC7S6 5.55 6.50 6.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 41: Clock-Capable Clock Input to Output Delay With MMCM(1) VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable clock input and OUTFF with MMCM.(2) XC7S6 1.03 1.03 1.03 ns XC7S15 1.03 1.03 1.03 ns XC7S25 1.00 1.00 1.00 ns XC7S50 1.00 1.00 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 42: Clock-Capable Clock Input to Output Delay With PLL(1) VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL. TICKOFPLLCC Clock-capable clock input and OUTFF with PLL.(2) XC7S6 0.85 0.85 0.85 ns XC7S15 0.85 0.85 0.85 ns XC7S25 0.83 0.83 0.83 ns XC7S50 0.83 0.83 0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Device Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted. Table 44: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 -1L Units Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 45: Clock-Capable Clock Input Setup and Hold With MMCM VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)(2) TPSMMCMCC/ No delay clock-capable clock input and TPHMMCMCC IFF(3) with MMCM. XC7S6 2.73/–0.59 3.27/–0.59 3.27/–0.59 ns XC7S15 2.73/–0.59 3.27/–0.59 3.27/–0.59 ns XC7S25 2.69/–0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 46: Clock-Capable Clock Input Setup and Hold With PLL VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)(2) TPSPLLCC/ TPHPLLCC No delay clock-capable clock input and IFF(3) with PLL. XC7S6 3.07/–0.17 3.69/–0.17 3.69/–0.17 ns XC7S15 3.07/–0.17 3.69/–0.17 3.69/–0.17 ns XC7S25 3.04/–0.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 48: Sample Window VCCINT Operating Voltage and Speed Grade Symbol TSAMP Description 1.0V Sampling error at receiver pins.(1) TSAMP_BUFIO Sampling error at receiver pins using BUFIO.(2) 0.95V Units -2 -1 -1L 0.64 0.70 0.70 ns 0.40 0.46 0.46 ns Notes: 1. 2. This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and process.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Additional Package Parameter Guidelines The parameters in this section provide the necessary values for calculating timing budgets for Spartan-7 FPGA clock transmitter and receiver data-valid windows. Table 49: Package Skew(1) Symbol Description Device XC7S6 XC7S15 XC7S25 XC7S50 XC7S75 TPKGSKEW Package skew.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics XADC Specifications The 7 Series FPGAs Overview (DS180) [Ref 1] and XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) [Ref 2] list the devices that contain a 7 series XADC dual 12-Bit 1 MSPS analog-to-digital converter.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 50: XADC Specifications (Cont’d) Parameter Symbol Comments/Conditions Min Typ Max Units 26 – 32 Cycles Conversion Rate(4) Conversion time: continuous tCONV Number of ADCCLK cycles. Conversion time: event tCONV Number of CLK cycles. – – 21 Cycles DRP clock frequency DCLK DRP clock frequency. 8 – 250 MHz ADC clock frequency ADCCLK Derived from DCLK. 1 – 26 MHz 40 – 60 % 1.20 1.25 1.30 V 1.2375 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Configuration Switching Characteristics Table 51: Configuration Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V Units -2 -1 -1L 5.00 5.00 5.00 ms, Max Power-on reset (50 ms ramp rate time). 10/50 10/50 10/50 ms, Min/Max Power-on reset (1 ms ramp rate time). 10/35 10/35 10/35 ms, Min/Max Program pulse width. 250.00 250.00 250.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 51: Configuration Switching Characteristics (Cont’d) VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V -2 0.95V -1 Units -1L TSMCSCCK/ TSMCCKCS CSI_B setup/hold. TSMWCCK/ TSMCCKW RDWR_B setup/hold. TSMCKCSO CSO_B clock to out (330 Ω pull-up resistor required). 7.00 7.00 7.00 ns, Max TSMCO D[31:00] clock to out in readback. 8.00 8.00 8.00 ns, Max FRBCCK Readback frequency. 100.00 100.00 100.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics eFUSE Programming Conditions Table 52 lists the programming conditions specifically for eFUSE. For more information, see the 7 Series FPGA Configuration User Guide (UG470) [Ref 10]. Table 52: eFUSE Programming Conditions(1) Symbol Description IFS VCCAUX supply current Tj Temperature range Min Typ Max Units – – 115 mA 15 – 125 °C Notes: 1. The FPGA must not be configured during eFUSE programming. References 1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Revision History The following table shows the revision history for this document: Date Version Description of Revisions 03/13/2019 1.9 Removed FTGB196 package from XA7S6, XA7S15, XA7S25, and XA7S50 devices in Table 49. 09/28/2018 1.8 Removed description of -1Q speed grade only being available in XA Spartan-7 FPGAs from second paragraph of Introduction. 07/31/2018 1.7 In Table 12, updated Vivado tools version to 2018.2.1.
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Date Version Description of Revisions 04/07/2017 1.1 Added 1.35V to Note 5 in Table 2. In Table 12, updated Vivado tools version to 2016.4. In Table 13, moved all speed grades for XC7S50 from Advance to Preliminary. Removed SFI-4.1 and SPI-4.2 from descriptions of SDR LVDS receiver and DDR LVDS receiver, respectively, in Table 15. In Table 25, changed TIDELAYRESOLUTION units from ps to µs. Removed BUFMR from Note 1 in Table 34.