Datasheet

Bits Name Description Type Reset
31:24 IMPLEMENTER Implementor code: 0x41 = ARM RO 0x41
23:20 VARIANT Major revision number n in the rnpm revision status:
0x0 = Revision 0.
RO 0x0
19:16 ARCHITECTURE Constant that defines the architecture of the processor:
0xC = ARMv6-M architecture.
RO 0xc
15:4 PARTNO Number of processor within family: 0xC60 = Cortex-M0+ RO 0xc60
3:0 REVISION Minor revision number m in the rnpm revision status:
0x1 = Patch 1.
RO 0x1
ICSR Register
Description
Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending
PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority
pended exception, check the vector number of the active exception.
Table 135. ICSR
Register
Bits Name Description Type Reset
31 NMIPENDSET Setting this bit will activate an NMI. Since NMI is the
highest priority exception, it will activate as soon as it is
registered.
NMI set-pending bit.
Write:
0 = No effect.
1 = Changes NMI exception state to pending.
Read:
0 = NMI exception is not pending.
1 = NMI exception is pending.
Because NMI is the highest-priority exception, normally the
processor enters the NMI
exception handler as soon as it detects a write of 1 to this
bit. Entering the handler then clears
this bit to 0. This means a read of this bit by the NMI
exception handler returns 1 only if the
NMI signal is reasserted while the processor is executing
that handler.
RW 0x0
30:29 Reserved. - - -
28 PENDSVSET PendSV set-pending bit.
Write:
0 = No effect.
1 = Changes PendSV exception state to pending.
Read:
0 = PendSV exception is not pending.
1 = PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV
exception state to pending.
RW 0x0
27 PENDSVCLR PendSV clear-pending bit.
Write:
0 = No effect.
1 = Removes the pending state from the PendSV
exception.
RW 0x0
RP2040 Datasheet
2.4. Cortex-M0+ 98