Datasheet

Table Of Contents
Description
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest
priority, and 3 is the lowest.
Table 129. NVIC_IPR3
Register
Bits Name Description Type Reset
31:30 IP_15 Priority of interrupt 15 RW 0x0
29:24 Reserved. - - -
23:22 IP_14 Priority of interrupt 14 RW 0x0
21:16 Reserved. - - -
15:14 IP_13 Priority of interrupt 13 RW 0x0
13:8 Reserved. - - -
7:6 IP_12 Priority of interrupt 12 RW 0x0
5:0 Reserved. - - -
NVIC_IPR4 Register
Description
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest
priority, and 3 is the lowest.
Table 130. NVIC_IPR4
Register
Bits Name Description Type Reset
31:30 IP_19 Priority of interrupt 19 RW 0x0
29:24 Reserved. - - -
23:22 IP_18 Priority of interrupt 18 RW 0x0
21:16 Reserved. - - -
15:14 IP_17 Priority of interrupt 17 RW 0x0
13:8 Reserved. - - -
7:6 IP_16 Priority of interrupt 16 RW 0x0
5:0 Reserved. - - -
NVIC_IPR5 Register
Description
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest
priority, and 3 is the lowest.
Table 131. NVIC_IPR5
Register
Bits Name Description Type Reset
31:30 IP_23 Priority of interrupt 23 RW 0x0
29:24 Reserved. - - -
23:22 IP_22 Priority of interrupt 22 RW 0x0
21:16 Reserved. - - -
15:14 IP_21 Priority of interrupt 21 RW 0x0
13:8 Reserved. - - -
RP2040 Datasheet
2.4. Cortex-M0+ 96