Datasheet

Table 123. NVIC_ICER
Register
Bits Name Description Type Reset
31:0 CLRENA Interrupt clear-enable bits.
Write:
0 = No effect.
1 = Disable interrupt.
Read:
0 = Interrupt disabled.
1 = Interrupt enabled.
RW 0x00000000
NVIC_ISPR Register
Description
The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.
Table 124. NVIC_ISPR
Register
Bits Name Description Type Reset
31:0 SETPEND Interrupt set-pending bits.
Write:
0 = No effect.
1 = Changes interrupt state to pending.
Read:
0 = Interrupt is not pending.
1 = Interrupt is pending.
Note: Writing 1 to the NVIC_ISPR bit corresponding to:
An interrupt that is pending has no effect.
A disabled interrupt sets the state of that interrupt to
pending.
RW 0x00000000
NVIC_ICPR Register
Description
Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently
pending.
Table 125. NVIC_ICPR
Register
Bits Name Description Type Reset
31:0 CLRPEND Interrupt clear-pending bits.
Write:
0 = No effect.
1 = Removes pending state and interrupt.
Read:
0 = Interrupt is not pending.
1 = Interrupt is pending.
RW 0x00000000
NVIC_IPR0 Register
Description
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest
priority, and 3 is the lowest.
Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.
These registers are only word-accessible
Table 126. NVIC_IPR0
Register
Bits Name Description Type Reset
31:30 IP_3 Priority of interrupt 3 RW 0x0
29:24 Reserved. - - -
RP2040 Datasheet
2.4. Cortex-M0+ 94