Datasheet

Table 120. SYST_CVR
Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:0 CURRENT Reads return the current value of the SysTick counter. This
register is write-clear. Writing to it with any value clears the
register to 0. Clearing this register also clears the
COUNTFLAG bit of the SysTick Control and Status
Register.
RW 0x000000
SYST_CALIB Register
Description
Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and
multiply.
Table 121.
SYST_CALIB Register
Bits Name Description Type Reset
31 NOREF If reads as 1, the Reference clock is not provided - the
CLKSOURCE bit of the SysTick Control and Status register
will be forced to 1 and cannot be cleared to 0.
RO 0x0
30 SKEW If reads as 1, the calibration value for 10ms is inexact (due
to clock frequency).
RO 0x0
29:24 Reserved. - - -
23:0 TENMS An optional Reload value to be used for 10ms (100Hz)
timing, subject to system clock skew errors. If the value
reads as 0, the calibration value is not known.
RO 0x000000
NVIC_ISER Register
Description
Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled,
asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt,
regardless of its priority.
Table 122. NVIC_ISER
Register
Bits Name Description Type Reset
31:0 SETENA Interrupt set-enable bits.
Write:
0 = No effect.
1 = Enable interrupt.
Read:
0 = Interrupt disabled.
1 = Interrupt enabled.
RW 0x00000000
NVIC_ICER Register
Description
Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.
RP2040 Datasheet
2.4. Cortex-M0+ 93