Datasheet

Table Of Contents
2.4.6. MPU
2.4.6.1. About the MPU
The MPU is a component for memory protection which allows the processor to support the ARMv6 Protected Memory
System Architecture model. The MPU provides full support for:
Eight unified protection regions.
Overlapping protection regions, with ascending region priority:
7 = highest priority.
0 = lowest priority.
Access permissions.
Exporting memory attributes to the system.
MPU mismatches and permission violations invoke the HardFault handler. See the ARMv6-M Architecture Reference
Manual for more information.
You can use the MPU to:
Enforce privilege rules.
Separate processes.
Manage memory attributes.
2.4.6.2. MPU register summary
Table 116 shows the MPU registers. Each of these registers is 32 bits wide.
Table 116. M0+ MPU
registers
Name Description
MPU_TYPE MPU Type Register.
MPU_CTRL MPU Control Register.
MPU_RNR MPU Region Number Register.
MPU_RBAR MPU Region Base Address Register.
MPU_RASR MPU Region Attribute and Size Register.
Note
See the ARMv6-M Architecture Reference Manual for more information about the MPU registers and their
addresses, access types, and reset values.
The MPU supports region sizes from 256-bytes to 4Gb, with 8-sub regions per region.
2.4.7. Debug
Basic debug functionality includes processor halt, single-step, processor core register access, Reset and HardFault Vector
Catch, unlimited software breakpoints, and full system memory access. See the ARMv6-M Architecture Reference
Manual.
The debug features for this device are:
A breakpoint unit supporting 4 hardware breakpoints.
A watchpoint unit supporting 2 watchpoints.
RP2040 Datasheet
2.4. Cortex-M0+ 90