Datasheet

Table Of Contents
2.4.5. NVIC
2.4.5.1. About the NVIC
External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority of each
interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low latency interrupt processing
and efficient processing of late arriving interrupts.
All NVIC registers are only accessible using word transfers. Any attempt to read or write a halfword or byte individually is
unpredictable.
NVIC registers are always little-endian.
Processor exception handling is described in Exceptions section.
2.4.5.1.1. SysTick timer
A 24-bit SysTick system timer, extends the functionality of both the processor and the NVIC and provides:
A 24-bit system timer (SysTick).
Additional configurable priority SysTick interrupt.
The SysTick timer uses a 1us pulse as a clock enable. This is generated in the watchdog block as timer_tick. Accuracy of
SysTick timing depends upon accuracy of this timer_tick. The SysTick timer can also run from the system clock (see
SYST_CALIB).
See the ARMv6-M Architecture Reference Manual for more information.
2.4.5.1.2. Low power modes
The implementation includes a WIC. This enables the processor and NVIC to be put into a very low-power sleep mode
leaving the WIC to identify and prioritize interrupts.
The processor fully implements the Wait For Interrupt (WFI), Wait For Event (WFE) and the Send Event (SEV) instructions.
In addition, the processor also supports the use of SLEEPONEXIT, that causes the processor core to enter sleep mode
when it returns from an exception handler to Thread mode. See the ARMv6-M Architecture Reference Manual for more
information.
2.4.5.2. NVIC register summary
Table 115 shows the NVIC registers. Each of these registers is 32 bits wide.
Table 115. M0+ NVIC
registers
Name Description
NVIC_ISER Interrupt Set-Enable Register.
NVIC_ICER Interrupt Clear-Enable Register.
NVIC_ISPR Interrupt Set-Pending Register.
NVIC_ICPR Interrupt Clear-Pending Register.
NVIC_IPR0 - NVIC_IPR7 Interrupt Priority Registers.
Note
See the List of Registers or ARMv6-M Architecture Reference Manual for more information about the NVIC registers
and their addresses, access types, and reset values.
RP2040 Datasheet
2.4. Cortex-M0+ 89