Datasheet

The processor implementation can TO DO (NICK): what do we have ? ensure that a fixed number of cycles are required for
the NVIC to detect an interrupt signal and the processor fetch the first instruction of the associated interrupt handler. If
this is done, the highest priority interrupt is jitter-free. See the documentation supplied by the processor implementer for
more information. #TO DO: (NICK) That will be us then #
To reduce interrupt latency and jitter, the Cortex-M0+ processor implements both interrupt late-arrival and interrupt tail-
chaining mechanisms, as defined by the ARMv6-M architecture. The worst case interrupt latency, for the highest priority
active interrupt in a zero wait-state system not using jitter suppression, is 15 cycles.
The processor exception model has the following implementation-defined behavior in addition to the architecture
specified behavior:
•
Exceptions on stacking from HardFault to NMI lockup at NMI priority.
•
Exceptions on unstacking from NMI to HardFault lockup at HardFault priority.
2.4.4. System control
2.4.4.1. System control register summary
Table 114 gives the system control registers. Each of these registers is 32 bits wide.
Table 114. M0+
System control
registers
Name Description
SYST_CSR SysTick Control and Status Register
SYST_RVR SysTick Reload Value Register
SYST_CVR SysTick Current Value Register
SYST_CALIB SysTick Calibration value Register
CPUID See CPUID Register
ICSR Interrupt Control State Register
AIRCR Application Interrupt and Reset Control Register
CCR Configuration and Control Register
SHPR2 System Handler Priority Register
SHPR3 System Handler Priority Register
SHCSR System Handler Control and State Register
VTOR Vector table Offset Register
ACTLR Auxiliary Control Register
Note
•
All system control registers are only accessible using word transfers. Any attempt to read or write a halfword or
byte is Unpredictable.
•
See the List of Registers or ARMv6-M Architecture Reference Manual for more information about the system
control registers, and their addresses and access types, and reset values.
2.4.4.1.1. CPUID Register
The CPUID contains the part number, version, and implementation information that is specific to the processor.
RP2040 Datasheet
2.4. Cortex-M0+ 88