Datasheet

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Address range Code Data Device

0x00000000 - 0x1fffffff

Yes Yes No

. Space reserved for Cortex-M0+ NVIC and debug components.

Note

Regions not marked as suitable for code behave as eXecute-Never (XN) and generate a HardFault exception if code

attempts to execute from this location.

See the ARMv6-M Architecture Reference Manual for more information about the memory model.

2.4.3.5. Processor core registers summary

Table 113 shows the processor core register set summary. Each of these registers is 32 bits wide.

Table 113. M0+

processor core

Name Description

R0-R12 R0-R12 are general-purpose registers for data operations.

MSP/PSP (R13) The Stack Pointer (SP) is register R13. In Thread mode, the

CONTROL register indicates the stack pointer to use, Main

Stack Pointer (MSP) or Process Stack Pointer (PSP).

LR (R14) The Link Register (LR) is register R14. It stores the return

information for subroutines, function calls, and exceptions.

PC (R15) The Program Counter (PC) is register R15. It contains the

current program address. PSR The Program Status

(IPSR). * Execution Program Status Register (EPSR). These

registers provide different views of the PSR.

PRIMASK The PRIMASK register prevents activation of all exceptions

with configurable priority.

CONTROL The CONTROL register controls the stack used, the code

privilege level, when the processor is in Thread mode.

Note

See the ARMv6-M Architecture Reference Manual for information about the processor core registers and their

addresses, access types, and reset values.

2.4.3.6. Exceptions

This section describes the exception model of the processor.

2.4.3.6.1. Exception handling

The processor implements advanced exception and interrupt handling, as described in the ARMv6-M Architecture

Reference Manual. To minimize interrupt latency, the processor abandons any load-multiple or store-multiple instruction

to take any pending interrupt. On return from the interrupt handler, the processor restarts the load-multiple or store-

multiple instruction from the beginning.

This means that software must not use load-multiple or store-multiple instructions when a device is accessed in a

memory region that is read-sensitive or sensitive to repeated writes. The software must not use these instructions in any

case where repeated reads or writes might cause inconsistent results or unwanted side-effects.

RP2040 Datasheet

2.4. Cortex-M0+ 87