Datasheet

Operation Description Assembler Cycles
Wait For Interrupt
WFI
2
f
Yield
YIELD
1
f
No operation
NOP
1
Barriers Instruction synchronization
ISB
3
Data memory
DMB
3
Data synchronization
DSB
3
Table Notes
a
2 if to AHB interface or SCS, 1 if to single-cycle I/O port.
b
N is the number of elements in the list.
c
N is the number of elements in the list including PC or LR.
d
2 if taken, 1 if not-taken.
e
Cycle count depends on processor and debug configuration.
f
Excludes time spent waiting for an interrupt or event.
g
Executes as NOP.
See the ARMv6-M Architecture Reference Manual for more information about the ARMv6-M Thumb instructions.
2.4.3.4. Memory model
The processor contains a bus matrix that arbitrates the processor core and Debug Access Port (DAP) memory accesses
to both the external memory system and to the internal NVIC and debug components.
Priority is always given to the processor to ensure that any debug accesses are as non-intrusive as possible. For a zero
wait-state system, all debug accesses to system memory, NVIC, and debug resources are completely non-intrusive for
typical code execution.
The system memory map is ARMv6-M architecture compliant, and is common both to the debugger and processor
accesses. Transactions are routed as follows:
•
All accesses below 0xd0000000 or above 0xefffffff appear as AHB-Lite transactions on the AHB-Lite master port of
the processor.
•
Acessses in the range 0xd0000000 to 0xdfffffff are handled by the SIO.
•
Accesses in the range 0xe0000000 to 0xefffffff are handled within the processor and do not appear on the AHB-Lite
master port of the processor.
The processor supports only word size accesses in the range 0xd0000000 - 0xefffffff.
Table 112 shows the code, data, and device suitability for each region of the default memory map. This is the memory
map used by implementations when the MPU is disabled. The attributes and permissions of all regions, except that
targeting the Cortex-M0+ NVIC and debug components, can be modified using an implemented MPU.
Table 112. M0+
Default memory map
usage
Address range Code Data Device
0xf0000000 - 0xffffffff
No No Yes
0xe0000000 - 0xefffffff
No No No
a
0xa0000000 - 0xdfffffff
No No Yes
0x60000000 - 0x9fffffff
Yes Yes No
0x40000000 - 0x5fffffff
No No Yes
0x20000000 - 0x3fffffff
Yes Yes No
RP2040 Datasheet
2.4. Cortex-M0+ 86