Datasheet

Table Of Contents
Operation Description Assembler Cycles
PC-relative
LDR Rd, <label>
2 or 1
a
SP-relative
LDR Rd, [SP, #<imm>]
2 or 1
a
Multiple, excluding base
LDM Rn!, {<loreglist>}
1+N
b
Multiple, including base
LDM Rn, {<loreglist>}
1+N
b
Store Word, immediate offset
STR Rd, [Rn, #<imm>]
2 or 1
a
Halfword, immediate offset
STRH Rd, [Rn, #<imm>]
2 or 1
a
Byte, immediate offset
STRB Rd, [Rn, #<imm>]
2 or 1
a
Word, register offset
STR Rd, [Rn, Rm]
2 or 1
a
Halfword, register offset
STRH Rd, [Rn, Rm]
2 or 1
a
Byte, register offset
STRB Rd, [Rn, Rm]
2 or 1
a
SP-relative
STR Rd, [SP, #<imm>]
2 or 1
a
Multiple
STM Rn!, {<loreglist>}
1+N
b
Push Push
PUSH {<loreglist>}
1+N
b
Push with link register
PUSH {<loreglist>, LR}
1+N
c
Pop Pop
POP {<loreglist>}
1+N
b
Pop and return
POP {<loreglist>, PC}
3+N
c
Branch Conditional
B<cc> <label>
1 or 2
d
Unconditional
B <label>
2
With link
BL <label>
3
With exchange
BX Rm
2
With link and exchange
BLX Rm
2
Extend Signed halfword to word
SXTH Rd, Rm
1
Signed byte to word
SXTB Rd, Rm
1
Unsigned halfword
UXTH Rd, Rm
1
Unsigned byte
UXTB Rd, Rm
1
Reverse Bytes in word
REV Rd, Rm
1
Bytes in both halfwords
REV16 Rd, Rm
1
Signed bottom half word
REVSH Rd, Rm
1
State change Supervisor Call
SVC #<imm>
-
e
Disable interrupts
CPSID i
1
Enable interrupts
CPSIE i
1
Read special register
MRS Rd, <specreg>
3
Write special register
MSR <specreg>, Rn
3
Breakpoint
BKPT #<imm>
-
e
Hint Send-Event
SEV
1
Wait For Event
WFE
2
f
RP2040 Datasheet
2.4. Cortex-M0+ 85