Datasheet

Operation Description Assembler Cycles
8-bit immediate
ADDS Rd, Rd, #<imm>
1
With carry
ADCS Rd, Rd, Rm
1
Immediate to SP
ADD SP, SP, #<imm>
1
Form address from SP
ADD Rd, SP, #<imm>
1
Form address from PC
ADR Rd, <label>
1
Subtract Lo and Lo
SUBS Rd, Rn, Rm
1
3-bit immediate
SUBS Rd, Rn, #<imm>
1
8-bit immediate
SUBS Rd, Rd, #<imm>
1
With carry
SBCS Rd, Rd, Rm
1
Immediate from SP
SUB SP, SP, #<imm>
1
Negate
RSBS Rd, Rn, #0
1
Multiply Multiply
MULS Rd, Rm, Rd
1
Compare Compare
CMP Rn, Rm
1
Negative
CMN Rn, Rm
1
Immediate
CMP Rn, #<imm>
1
Logical AND
ANDS Rd, Rd, Rm
1
Exclusive OR
EORS Rd, Rd, Rm
1
OR
ORRS Rd, Rd, Rm
1
Bit clear
BICS Rd, Rd, Rm
1
Move NOT
MVNS Rd, Rm
1
AND test
TST Rn, Rm
1
Shift Logical shift left by immediate
LSLS Rd, Rm, #<shift>
1
Logical shift left by register
LSLS Rd, Rd, Rs
1
Logical shift right by immediate
LSRS Rd, Rm, #<shift>
1
Logical shift right by register
LSRS Rd, Rd, Rs
1
Arithmetic shift right
ASRS Rd, Rm, #<shift>
1
Arithmetic shift right by register
ASRS Rd, Rd, Rs
1
Rotate Rotate right by register
RORS Rd, Rd, Rs
1
Load Word, immediate offset
LDR Rd, [Rn, #<imm>]
2 or 1
a
Halfword, immediate offset
LDRH Rd, [Rn, #<imm>]
2 or 1
a
Byte, immediate offset
LDRB Rd, [Rn, #<imm>]
2 or 1
a
Word, register offset
LDR Rd, [Rn, Rm]
2 or 1
a
Halfword, register offset
LDRH Rd, [Rn, Rm]
2 or 1
a
Signed halfword, register offset
LDRSH Rd, [Rn, Rm]
2 or 1
a
Byte, register offset
LDRB Rd, [Rn, Rm]
2 or 1
a
Signed byte, register offset
LDRSB Rd, [Rn, Rm]
2 or 1
a
RP2040 Datasheet
2.4. Cortex-M0+ 84