Datasheet

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Any WFE wakeup event, or the execution of an exception return instruction, sets the Event Register.
A WFE instruction clears the Event Register.
Software cannot read or write the value of the Event Register directly.
The Send-Event instruction
The Send-Event (SEV) instruction causes an event to be signaled to the other processor. The Send-Event instruction
generates a wakeup event.
The Wait For Event instruction
The action of the WFE instruction depends on the state of the Event Register:
If the Event Register is set, the instruction clears the register and returns immediately.
If the Event Register is clear the processor can suspend execution and enter a low-power state. It can remain in that
state until the processor detects a WFE wakeup event or a reset. When the processor detects a WFE wakeup event, the
WFE instruction completes.
WFE wakeup events can occur before a WFE instruction is issued. Software using the WFE mechanism must tolerate
spurious wake up events, including multiple wakeups.
2.4.2.8.3. Wait For Interrupt
RP2040 supports Wait For Interrupt through the hint instruction, WFI.
When a processor issues a WFI instruction it can suspend execution and enter a low-power state. It can remain in that
state until the processor detects one of the following WFI wake up events:
A reset.
An asynchronous exception at a priority that, if PRIMASK.PM was set to 0, would preempt any currently active
exceptions.
Note
If PRIMASK.PM is set to 1, an asynchronous exception that has a higher group priority than any active exception
results in a WFI instruction exit. If the group priority of the exception is less than or equal to the execution group
priority, the exception is ignored.
If debug is enabled, a debug event.
A WFI wakeup event.
The WFI instruction completes when the hardware detects a WFI wake up event, or earlier if the implementation chooses.
The processor recognizes WFI wake up events only after issuing the WFI instruction.
2.4.2.8.4. Wakeup Interrupt Controller
The Wakeup Interrupt Controller (WIC) is used to wake the processor from a DEEPSLEEP state as controlled by the SCR
register. In a DEEPSLEEP state clocks to the processor core and NVIC are not running. It can take a few cycles to wake
from a DEEPSLEEP state.
The WIC takes inputs from the receive event signal (from the other processor), 32 interrupts lines, and NMI.
For more power saving, RP2040 supports system level power saving modes as defined in Section 2.10 which also
includes code examples.
2.4.2.9. Reset Control
The Cortex M0+ Reset Control block controls the following resets:
RP2040 Datasheet
2.4. Cortex-M0+ 82