Datasheet

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A processor clock containing the core and associated interfaces
Control is limited to clock enable/disable. When enabled, all domains run at the same clock speed.
The PMU also interfaces with the WIC, to ensure that power-down and wake-up behaviors are transparent to software and
work with clocking and sleeping requirements. This includes SLEEP or DEEPSLEEP support as controlled in SCR register.
2.4.2.8.1. Power Management
RP2040 ARM Cortex M0+ uses ARMv6-M which supports the use of Wait For Interrupt (WFI) and Wait For Event (WFE)
instructions as part of system power management:
WFI provides a mechanism for hardware support of entry to one or more sleep states. Hardware can suspend execution
until a wakeup event occurs.
WFE provides a mechanism for software to suspend program execution until a wakeup condition occurs with minimal or no
impact on wakeup latency. Both WFI and WFE are hint instructions that might have no effect on program execution.
Normally, they are used in software idle loops that resume program execution only after an interrupt or event of interest
occurs.
NOTE
Code using WFE and WFI must handle any spurious wakeup events caused by a debug halt or other reasons.
Refer to the SDK and ARMv6-M guide for further information.
2.4.2.8.2. Wait For Event and Send Event
RP2040 can support software-based synchronization to system events using the Send-Event (SEV) and WFE hint
instructions. Software can:
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use the WFE instruction to indicate that it is able to suspend execution of a process or thread until an event occurs,
permitting hardware to enter a low power state.
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rely on a mechanism that is transparent to software and provides low latency wakeup.
The WFE mechanism relies on hardware and software working together to achieve energy saving. For example, stalling
execution of a processor until a device or another processor has set a flag:
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the hardware provides the mechanism to enter the WFE low-power state.
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software enters a polling loop to determine when the flag is set:
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the polling processor issues a WFE instruction as part of a polling loop if the flag is clear.
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an event is generated (hardware interrupt or Send-Event instruction from another processor) when the flag is set.
WFE wake up events
The following events are WFE wake up events:
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the execution of an SEV instruction on the other processor
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any exception entering the pending state if SEVONPEND in the System Control Register is set to 1.
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an asynchronous exception at a priority that preempts any currently active exceptions.
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a debug event with debug enabled.
The Event Register
The Event Register is a single bit register. When set, an Event Register indicates that an event has occurred, since the
register was last cleared, that might prevent the processor having to suspend operation on issuing a WFE instruction. The
following conditions apply to the Event Register:
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A reset clears the Event Register.
RP2040 Datasheet
2.4. Cortex-M0+ 81