Datasheet

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Support for unlimited software breakpoints using BKPT instruction.
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Non-intrusive access to core peripherals and zero-waitstate system slaves through a compact bus matrix. A
debugger can access these devices, including memory, even when the processor is running.
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Full access to core registers when the processor is halted.
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CoreSight compliant debug access through a Debug Access Port (DAP) supporting Serial Wire debug connections.
2.4.2.4.1. Debug Access Port
The processor is implemented with a low gate count Debug Access Port (DAP). The low gate count Debug Access Port
(DAP) provides a Serial Wire debug-port, and connects to the processor slave port to provide full system-level debug
access. For more information on DAP, see the ADI v5.1 version of the ARM Debug Interface v5, Architecture Specification
2.4.2.5. MPU features
Memory Protection Unit (MPU) features are:
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Eight user-configurable memory regions.
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Eight sub-region disables per region.
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Execute never (XN) support.
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Default memory map support.
Further details available in Section 2.4.6.
2.4.2.6. AHB-Lite interface
Transactions on the AHB-Lite interface are always marked as non-sequential. Processor accesses and debug accesses
share the external interface to external AHB peripherals. The processor accesses take priority over debug accesses. Any
vendor specific components can populate this bus.

NOTE
Instructions are only fetched using the AHB-Lite interface. To optimize performance, the Cortex-M0+ processor
fetches ahead of the instruction it is executing. To minimize power consumption, the fetch ahead is limited to a
maximum of 32 bits.
2.4.2.7. Single-cycle I/O port
The processor implements a single-cycle I/O port that provides high speed access to tightly-coupled peripherals, such as
general-purpose-I/O (GPIO). The port is accessible both by loads and stores from either the processor or the debugger.
You cannot execute code from the I/O port.
2.4.2.8. Power Management Unit
Each processor has its own Power Management Unit (PMU) which allows power saving by turning off clocks to parts of
the processor core. There are no separate power domains on RP2040.
The PMU runs from the processor clock which is controlled from the chip level clocks block. The PMU can control the
following clock domains within the processor:
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A debug clock containing the processor debug resources and the rest of the DAP.
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A system clock containing the NVIC.
RP2040 Datasheet
2.4. Cortex-M0+ 80