Datasheet

Cortex-M0+ subsystem
Clock
PMU MPUCortex M0+ Core
RESET CTRL
WIC DAP
Breakpoint and
watchpoint unit
Debugger
interface
NVIC
AHB-Lite Master
Single cycle IO Port
Serial Wire Debug
Reset
Interrupts
Bus Interface
HCLK
FCLK
DCLK
Figure 11. Cortex M0+
Functional block
diagram
2.4.2.2. Features
The M0+ features:
•
The ARMv6-M Thumb® instruction set.
•
Thumb-2 technology.
•
An ARMv6-M compliant 24-bit SysTick timer.
•
A 32-bit hardware multiplier. This is the standard single-cycle multiplier
•
The ability to have deterministic, fixed-latency, interrupt handling.
•
Load/store multiple instructions that can be abandoned and restarted to facilitate rapid interrupt handling.
•
C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-
ABI) compliant exception model that enables the use of pure C functions as interrupt handlers.
•
Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from
interrupt sleep-on-exit feature.
2.4.2.3. NVIC features
The Nested Vectored Interrupt Vontroller (NVIC) features are:
•
26 external interrupt inputs, each with four levels of priority.
•
Dedicated Non-Maskable Interrupt (NMI) input (which can be driven from any standard interrupt source)
•
Support for both level-sensitive and pulse-sensitive interrupt lines.
•
Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.
•
Relocatable vector table.
Further details available in Section 2.4.5.
2.4.2.4. Debug features
Debug features are:
•
Four hardware breakpoints.
•
Two watchpoints.
•
Program Counter Sampling Register (PCSR) for non-intrusive code profiling.
•
Single step and vector catch capabilities.
RP2040 Datasheet
2.4. Cortex-M0+ 79