Datasheet

2.4.1.2. Configuration
Each processor is configured with the following features:
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Architectural clock gating (for power saving)
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Little Endian bus access
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Four Breakpoints
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Debug support (via 2-wire debug pins SWD/SWCLK)
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32-bit instruction fetch (to match 32-bit data bus)
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IOPORT (for low latency access to local peripherals (see SIO)
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26 interrupts
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8 MPU regions
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All registers reset on powerup
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Fast multiplier (MULS 32x32 single cycle)
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SysTick timer
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Vector Table Offset Register (VTOR)
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34 WIC (Wake-up Interrupt Controller) lines (32 IRQ and NMI, RXEV)
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DAP feature: Halt event support
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DAP feature: SerialWire debug interface (protocol 2 with multidrop support)
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DAP feature: Micro Trace Buffer (MTB) is not implemented
Architectural clock gating allows the processor core to support SLEEP and DEEPSLEEP power states by disabling the
clock to parts of the processor core. Note that power gating is not supported.
Each M0+ core has its own interrupt controller which can individually mask out interrupt sources as required. The same
interrupts are routed to both M0+ cores.
2.4.1.3. ARM architecture
The processor implements the ARMv6-M architecture profile. See the ARMv6-M Architecture Reference Manual, and for
further details refer to the ARM Cortex M0+ Technical Reference Manual.
2.4.2. Functional Description
2.4.2.1. Overview
The Cortex-M0+ processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and
includes an NVIC component. It also has hardware debug, single-cycle I/O interfacing, and memory-protection
functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processors.
Figure 11 shows the functional blocks of the processor and surrounding blocks.
RP2040 Datasheet
2.4. Cortex-M0+ 78