Datasheet

has locked up, for example if code has been programmed into flash which permanently halts the system clock: in such a
case, the normal debugger can not communicate with the processors to return the system to a working state, so more
drastic action is needed. A rescue is invoked by setting the CDBGPWRUPREQ bit in the Rescue DP’s CTRL/STAT register.
This causes a hard reset of the chip (functionally similar to a power-on-reset), and sets a flag in the Chip Level Reset block
to indicate that a rescue reset took place. The bootrom checks this flag almost immediately in the initial boot process
(before watchdog, flash or USB boot), acknowledges by clearing the bit, then halts the processor. This leaves the system
in a safe state, with the system clock running, so that the debugger can reattach to the cores and load fresh code.
TO DO: LIAM: link to example of how to do this in the getting started/hardare design or similar book
2.4. Cortex-M0+
ARM Documentation
Excerpted from the Cortex-M0+ Technical Reference Manual. Used with permission.
The ARM Cortex-M0+ processor is a very low gate count, highly energy efficient processor that is intended for
microcontroller and deeply embedded applications that require an area optimized, low-power processor.
2.4.1. Features
The ARM Cortex-M0+ processor features and benefits are:
•
Tight integration of system peripherals reduces area and development costs.
•
Thumb instruction set combines high code density with 32-bit performance.
•
Support for single-cycle I/O access.
•
Power control optimization of system components.
•
Integrated sleep modes for low-power consumption.
•
Fast code execution enables running the processor with a slower clock or increasing sleep mode time.
•
Optimized code fetching for reduced flash and ROM power consumption.
•
Hardware multiplier.
•
Deterministic, high-performance interrupt handling for time-critical applications.
•
Deterministic instruction cycle timing.
•
Support for system level debug authentication.
•
Serial Wire Debug reduces the number of pins required for debugging.
2.4.1.1. Interfaces
The interfaces included in the processor for external access include:
•
External AHB-Lite interface to busfabric
•
Debug Access Port (DAP)
•
Single-cycle I/O Port to SIO peripherals
RP2040 Datasheet
2.4. Cortex-M0+ 77