Datasheet

Table 109.
SPINLOCK31 Register
Bits Name Description Type Reset
31:0 NONAME Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously claim the
lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the same lock
simultaneously, core 0 wins.
The value returned on success is 0x1 << lock number.
RO 0x80000000
2.3.2. Interrupts
Each core is equipped with a standard ARM Nested Vectored Interrupt Controller (NVIC) which has 32 interrupt inputs.
Each NVIC has the same interrupts routed to it, with the exception of the GPIO interrupts: there is one GPIO interrupt per
bank, per core. These are completely independent, so e.g. core 0 can be interrupted by GPIO 0 in bank 0, and core 1 by
GPIO 1 in the same bank.
On RP2040, only the lower 26 IRQ signals are connected on the NVIC, and IRQs 26 to 31 are tied to zero (never firing). The
core can still be forced to enter the relevant interrupt handler by writing bits 26 to 31 in the NVIC ISPR register.
Table 110. Interrupts
IRQ Interrupt Source IRQ Interrupt Source IRQ Interrupt Source IRQ Interrupt Source IRQ Interrupt Source
0
TIMER_IRQ_0
6
XIP_IRQ
12
DMA_IRQ_1
18
SPI0_IRQ
24
I2C1_IRQ
1
TIMER_IRQ_1
7
PIO0_IRQ_0
13
IO_IRQ_BANK0
19
SPI1_IRQ
25
RTC_IRQ
2
TIMER_IRQ_2
8
PIO0_IRQ_1
14
IO_IRQ_QSPI
20
UART0_IRQ
3
TIMER_IRQ_3
9
PIO1_IRQ_0
15
SIO_IRQ_PROC0
21
UART1_IRQ
4
PWM_IRQ_WRAP
10
PIO1_IRQ_1
16
SIO_IRQ_PROC1
22
ADC_IRQ_FIFO
5
USBCTRL_IRQ
11
DMA_IRQ_0
17
CLOCKS_IRQ
23
I2C0_IRQ
The 26 system IRQ signals are masked (NMI mask) and then ORed together creating the NMI signal for the core. The NMI
mask for each core can be configured using PROC0_NMI_MASK and PROC1_NMI_MASK in the Syscfg register block.
Each of these registers has one bit for each system interrupt, and the each core’s NMI is asserted if a system interrupt is
asserted and the corresponding NMI mask bit is set for that core.

CAUTION
If the watchdog is armed, and some bits are set on the core 1 NMI mask, the RESETS block (and hence Syscfg) should
be included in the watchdog reset list. Otherwise, following a watchdog event, core 1 NMI may be asserted when the
core enter the bootrom. It is safe for core 0 to take an NMI when entering the bootrom (the handler will clear the NMI
mask).
2.3.3. Event Signals
The Cortex-M0+ can enter a sleep state until an "event" (or interrupt) takes place, using the WFE instruction. It can also
generate events, using the SEV instruction. On RP2040 the event signals are cross-wired between the two processors, so
that an event sent by one processor will be received on the other.
RP2040 Datasheet
2.3. Processor subsystem 75