Datasheet

Description
Values written here are atomically added to ACCUM0
Reading yields lane 0’s raw shift and mask value (BASE0 not added).
Table 75.
INTERP1_ACCUM0_AD
D Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:0 NONAME RW 0x000000
INTERP1_ACCUM1_ADD Register
Description
Values written here are atomically added to ACCUM1
Reading yields lane 1’s raw shift and mask value (BASE1 not added).
Table 76.
INTERP1_ACCUM1_AD
D Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:0 NONAME RW 0x000000
INTERP1_BASE_1AND0 Register
Description
On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
Table 77.
INTERP1_BASE_1AND
0 Register
Bits Name Description Type Reset
31:0 NONAME WO 0x00000000
SPINLOCK0 Registers
Table 78. SPINLOCK0
Registers
Bits Name Description Type Reset
31:0 NONAME Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously claim the
lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the same lock
simultaneously, core 0 wins.
The value returned on success is 0x1 << lock number.
RO 0x00000001
SPINLOCK1 Register
RP2040 Datasheet
2.3. Processor subsystem 64