Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
5.2.2. Pin Definitions
5.2.2.1. Pin Types
In the following GPIO Pin table, the pin types are defined as shown below.
Table 637. Pin Types
Pin Type Direction Description
Digital In Input only Standard Digital. Programmable Pull-Up, Pull-Down, Slew Rate, Schmitt
Trigger and Drive Strength. Default Drive Strength is 4mA.
Digital IO Bi-directional
Digital In (FT) Input only Fault Tolerant Digital. These pins are described as Fault Tolerant,
which in this case means that very little current flows into the pin whilst
it is below 3.63V and IOVDD is 0V. There is also enhanced ESD
protection on these pins. Programmable Pull-Up, Pull-Down, Slew Rate,
Schmitt Trigger and Drive Strength. Default Drive Strength is 4mA.
Digital IO (FT) Bi-directional
Digital IO / Analogue Bi-directional (digital),
Input (Analogue)
Standard Digital and ADC input. Programmable Pull-Up, Pull-Down,
Slew Rate, Schmitt Trigger and Drive Strength. Default Drive Strength is
4mA.
USB IO Bi-directional These pins are for USB use, and contain internal pull-up and pull-down
resistors, as per the USB specification. Note that external 27Ω series
resistors are required for USB operation.
Analogue (XOSC) Oscillator input pins for attaching a 12MHz crystal. Alternatively, XIN
may be driven by a square wave.
5.2.2.2. Pin List
Table 638. GPIO pins
Name Number Type Power Domain Reset State Description
GPIO0 2 Digital IO (FT) IOVDD Pull-Down User IO
GPIO1 3 Digital IO (FT) IOVDD Pull-Down User IO
GPIO2 4 Digital IO (FT) IOVDD Pull-Down User IO
GPIO3 5 Digital IO (FT) IOVDD Pull-Down User IO
GPIO4 6 Digital IO (FT) IOVDD Pull-Down User IO
GPIO5 7 Digital IO (FT) IOVDD Pull-Down User IO
GPIO6 8 Digital IO (FT) IOVDD Pull-Down User IO
GPIO7 9 Digital IO (FT) IOVDD Pull-Down User IO
GPIO8 11 Digital IO (FT) IOVDD Pull-Down User IO
GPIO9 12 Digital IO (FT) IOVDD Pull-Down User IO
GPIO10 13 Digital IO (FT) IOVDD Pull-Down User IO
GPIO11 14 Digital IO (FT) IOVDD Pull-Down User IO
GPIO12 15 Digital IO (FT) IOVDD Pull-Down User IO
GPIO13 16 Digital IO (FT) IOVDD Pull-Down User IO
GPIO14 17 Digital IO (FT) IOVDD Pull-Down User IO
GPIO15 18 Digital IO (FT) IOVDD Pull-Down User IO
RP2040 Datasheet
5.2. Pinout 630