Datasheet

Table 70.
INTERP1_PEEK_LANE
0 Register
Bits Name Description Type Reset
31:0 NONAME RO 0x00000000
INTERP1_PEEK_LANE1 Register
Description
Read LANE1 result, without altering any internal state (PEEK).
Table 71.
INTERP1_PEEK_LANE
1 Register
Bits Name Description Type Reset
31:0 NONAME RO 0x00000000
INTERP1_PEEK_FULL Register
Description
Read FULL result, without altering any internal state (PEEK).
Table 72.
INTERP1_PEEK_FULL
Register
Bits Name Description Type Reset
31:0 NONAME RO 0x00000000
INTERP1_CTRL_LANE0 Register
Description
Control register for lane 0
Table 73.
INTERP1_CTRL_LANE
0 Register
Bits Name Description Type Reset
31:26 Reserved. - - -
25 OVERF Set if either OVERF0 or OVERF1 is set. RO 0x0
24 OVERF1 Indicates if any masked-off MSBs in ACCUM1 are set. RO 0x0
23 OVERF0 Indicates if any masked-off MSBs in ACCUM0 are set. RO 0x0
22 CLAMP Only present on INTERP1 on each core. If CLAMP mode is
enabled:
- LANE0 result is shifted and masked ACCUM0, clamped by
a lower bound of
BASE0 and an upper bound of BASE1.
- Signedness of these comparisons is determined by
LANE0_CTRL_SIGNED
RW 0x0
21 Reserved. - - -
20:19 FORCE_MSB ORed into bits 29:28 of the lane result presented to the
processor on the bus.
No effect on the internal 32-bit datapath. Handy for using a
lane to generate sequence
of pointers into flash or SRAM.
RW 0x0
18 ADD_RAW If 1, mask + shift is bypassed for LANE0 result. This does
not affect FULL result.
RW 0x0
17 CROSS_RESULT If 1, feed the opposite lane’s result into this lane’s
accumulator on POP.
RW 0x0
RP2040 Datasheet
2.3. Processor subsystem 62