Datasheet

Table Of Contents
0000_0010 dma_tx_req is asserted when two or less data entries are present in the transmit FIFO
0000_1101 dma_tx_req is asserted when 13 or less data entries are present in the transmit FIFO
0000_1110 dma_tx_req is asserted when 14 or less data entries are present in the transmit FIFO
0000_1111 dma_tx_req is asserted when 15 or less data entries are present in the transmit FIFO
Table 607 provides description for different DMA Receive Data Level values.
Table 607. DMA
Receive Data Level
(DMARDL) Decode
Value
DMARDL Value Description
0000_0000 dma_rx_req is asserted when one or more data entries are present in the receive FIFO
0000_0001 dma_rx_req is asserted when two or more data entries are present in the receive FIFO
0000_0010 dma_rx_req is asserted when three or more data entries are present in the receive FIFO
0000_1101 dma_rx_req is asserted when 14 or more data entries are present in the receive FIFO
0000_1110 dma_rx_req is asserted when 15 or more data entries are present in the receive FIFO
0000_1111 dma_rx_req is asserted when 16 data entries are present in the receive FIFO
4.11.11.1. Overview of Operation
As a block flow control device, the DMA Controller is programmed by the processor with the number of data items (block
size) that are to be transmitted or received by the DW_apb_ssi.
The block is broken into a number of transactions, each initiated by a request from the DW_apb_ssi. The DMA Controller
must also be programmed with the number of data items (in this case, DW_apb_ssi FIFO entries) to be transferred for
each DMA request. This is also known as the burst transaction length.
Figure 160 shows a single block transfer, where the block size programmed into the DMA Controller is 12 and the burst
transaction length is set to four. In this case, the block size is a multiple of the burst transaction length; therefore, the DMA
block transfer consists of a series of burst transactions.
TO DO: Liam: to check/review/change/remove DMA register settings here
12 Data Items
12 Data Items
4 Data Items4 Data Items 4 Data Items
DMA
Multi-block Transfer
Level
DMA
Block
Level
DMA Burst
Transaction 2
DMA Burst
Transaction 1
DMA Burst
Transaction 3
Figure 160.
Breakdown of DMA
Transfer into Burst
Transactions. Block
size,
DMA.CTLx.BLOCKS
_TS = 12. Number of
data items per source
burst transaction,
DMA.CTLx.SRC_MS
IZE = 4. SSI receive
FIFO watermark level,
SSI.DMARDLR + 1 =
DMA.CTLx.SRC_MS
IZE = 4
RP2040 Datasheet
4.11. SSI 618