Datasheet

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D1
D1
pclk
xip_en
psel
penable
paddr
pready
prdata[31:0]
ss_x_n
sclk_out
txd[7:0]
rxd[7:0]
Figure 159. Typical
Read Operation in XIP
Mode
4.11.11. DMA Controller Interface
The DW_apb_ssi has built-in DMA capability; it has a handshaking interface to a DMA Controller to request and control
transfers. The APB bus is used to perform the data transfer to or from the DMA.

NOTE
When the DW_apb_ssi interfaces to the DMA controller, the DMA controller is always a flow controller; that is, it
controls the block size. This must be programmed by software in the DMA controller.
The DW_apb_ssi uses two DMA channels, one for the transmit data and one for the receive data. The DW_apb_ssi has
these DMA registers:
DMACR
Control register to enable DMA operation.
DMATDLR
Register to set the transmit the FIFO level at which a DMA request is made.
DMARDLR
Register to set the receive FIFO level at which a DMA request is made.
The DW_apb_ssi uses the following handshaking signals to interface with the DMA controller.
•
dma_tx_req
•
dma_tx_single
•
dma_tx_ack
•
dma_rx_req
•
dma_tx_req
•
dma_tx_single
•
dma_tx_ack
•
dma_rx_req
To enable the DMA Controller interface on the DW_apb_ssi, you must write the DMA Control Register (DMACR). Writing a
1 into the TDMAE bit field of DMACR register enables the DW_apb_ssi transmit handshaking interface. Writing a 1 into the
RDMAE bit field of the DMACR register enables the DW_apb_ssi receive handshaking interface.
Table 606 provides description for different DMA transmit data level values.
Table 606. DMA
Transmit Data Level
(DMATDL) Decode
Value
DMATDL Value Description
0000_0000 dma_tx_req is asserted when zero data entries are present in the transmit FIFO
0000_0001 dma_tx_req is asserted when one or less data entry is present in the transmit FIFO
RP2040 Datasheet
4.11. SSI 617