Datasheet

4.11.10.4.3. Advanced I/O Mapping for Enhanced SPI Modes
The Input/Output mapping for enhanced SPI modes (dual, and quad) is hardcoded inside the DW_apb_ssi. The rxd[1]
signal will be used to sample incoming data in standard SPI mode of operation.
For other protocols (such as SSP and Microwire), the I/O mapping remains the same. Therefore, it is easy for other
protocols to connect with any device that supports Dual/Quad SPI operation because other protocols do not require a
MUX logic to exist outside the design.
Figure 153 hows the I/O mapping of DW_apb_ssi in Quad mode with another SPI device that supports the Quad mode. As
illustrated in Figure 153, the IO[1] pin is used as DO in standard SPI mode of operation and it is connected to rxd[1] pin,
which will be sampling the input in the standard mode of operation.
DW_apb_ssi SPI slave Device
IO[3]
txd[3]
rxd[3]
txd[2]
rxd[2]
txd[1]
rxd[1]
txd[0]
rxd[0]
IO[2]
IO[1]/DO
IO[0]/DIIO Buffer
IO Buffer
IO Buffer
IO Buffer
Figure 153. Advanced
I/O Mapping in Quad
SPI Modes
4.11.10.5. Dual Data-Rate (DDR) Support in SPI Operation
In standard operations, data transfer in SPI modes occur on either the positive or negative edge of the clock. For improved
throughput, the dual data-rate transfer can be used for reading or writing to the memories.
The DDR mode supports the following modes of SPI protocol:
•
SCPH=0 & SCPOL=0 (Mode 0)
•
SCPH=1 & SCPOL=1 (Mode 3)
DDR commands enable data to be transferred on both edges of clock. Following are the different types of DDR
commands:
•
Address and data are transmitted (or received in case of data) in DDR format, while instruction is transmitted in
standard format.
•
Instruction, address, and data are all transmitted or received in DDR format.
The DDR_EN (SPI_CTRLR0[16]) bit is used to determine if the Address and data have to be transferred in DDR mode and
INST_DDR_EN (SPI_CTRLR0[17]) bit is used to determine if Instruction must be transferred in DDR format. These bits are
only valid when the CTRLR0.SPI_FRF bit is set to be in Dual, or Quad mode.
Figure 154 describes a DDR write transfer where instructions are continued to be transmitted in standard format. In
Figure 154, the value of N will be 7 if CTRLR0.SPI_FRF is set to 11b, 3 if CTRLR0.SPI_FRF is set to 10b , and 1 if
CTRLR0.SPI_FRF is set to 01b.
RP2040 Datasheet
4.11. SSI 614