Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
0
Tx FIFO Buffer
FIFO Status Prior to
Transfer
FIFO Status on
Completion of Transfer
Rx FIFO Buffer
MWHS
MWCR
Location n
Location 3
Location 2
Location 1
Location 0
Location n
Location 3
Location 2
Location 1
Location 0
Write DR
NULL
Data Word(1) SHIFT LOGIC
Ctrl Word(1)
Tx Data(0)
Ctrl Word(0)
Rx FIFO Empty
1
MDD
0
MWMOD
rxd
txd
NULL
NULL
NULL
NULL
NULL
Tx FIFO Empty
Figure 139. FIFO
Status for Continuous
Microwire Transfer
(transmitting data
frame)
The Microwire handshaking interface can also be enabled for DW_apb_ssi master write operations to external serial-slave
devices. To enable the handshaking interface, you must write 1 into the MHS bit field (bit 2) on the MWCR register. When
MHS is set to 1, the DW_apb_ssi serial master checks for a ready status from the slave device before completing the
transfer, or transmitting the next control word for continuous transfers.
Figure 140 shows an example of a continuous Microwire transfer with the handshaking interface enabled.
sclk_out
txd
rxd
ss_0_n
ssi_oe_n
MSB LSB MSB LSB MSB LSB LSB
Start
Bit
ReadyBusy ReadyBusy
MSB
Control word 0 Control word 1Data word 0 Data word 1
Figure 140.
Continuous Microwire
Transfer with
Handshaking
(transmitting data
frame)
After the first data word has been transmitted to the serial-slave device, the DW_apb_ssi master polls the rxd input waiting
for a ready status from the slave device. Upon reception of the ready status, the DW_apb_ssi master begins transmission
of the next control word. After transmission of the last data frame has completed, the DW_apb_ssi master transmits a
start bit to clear the ready status of the slave device before completing the transfer. The FIFO status for this transfer is the
same as in Figure 139, except that the MWHS bit field is set (1).
To transmit a control word (not followed by data) to a serial-slave device from the DW_apb_ssi master, there must be only
one entry in the transmit FIFO buffer. It is impossible to transmit two control words in a continuous transfer, as the shift
logic in the DW_apb_ssi treats the second control word as a data word. When the DW_apb_ssi master transmits only a
control word, the MDD bit field (bit 1 of MWCR register) must be set (1).
In the example shown in Figure 141 and in the timing diagram in Figure 142, the handshaking interface is enabled. If the
handshaking interface is disabled (MHS=0), the transfer is terminated by the DW_apb_ssi master one sclk_out cycle after
the LSB of the control word is captured by the slave device.
1
Tx FIFO Buffer
FIFO Status Prior to
Transfer
FIFO Status on
Completion of Transfer
Rx FIFO Buffer
MWHS
MWCR
Location n
Location 3
Location 2
Location 1
Location 0
Location n
Location 3
Location 2
Location 1
Location 0
Write DR
NULL
NULL SHIFT LOGIC
NULL
NULL
Ctrl Word(0)
Rx FIFO Empty
1
MDD
0
MWMOD
rxd
txd
NULL
NULL
NULL
NULL
NULL
Tx FIFO Empty
Figure 141. FIFO
Status for Microwire
Control Word Transfer
RP2040 Datasheet
4.11. SSI 609