Datasheet

Table Of Contents
INTERP0_ACCUM0_ADD Register
Description
Values written here are atomically added to ACCUM0
Reading yields lane 0’s raw shift and mask value (BASE0 not added).
Table 59.
INTERP0_ACCUM0_AD
D Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:0 NONAME RW 0x000000
INTERP0_ACCUM1_ADD Register
Description
Values written here are atomically added to ACCUM1
Reading yields lane 1’s raw shift and mask value (BASE1 not added).
Table 60.
INTERP0_ACCUM1_AD
D Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:0 NONAME RW 0x000000
INTERP0_BASE_1AND0 Register
Description
On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
Table 61.
INTERP0_BASE_1AND
0 Register
Bits Name Description Type Reset
31:0 NONAME WO 0x00000000
INTERP1_ACCUM0 Register
Description
Read/write access to accumulator 0
Table 62.
INTERP1_ACCUM0
Register
Bits Name Description Type Reset
31:0 NONAME RW 0x00000000
INTERP1_ACCUM1 Register
Description
Read/write access to accumulator 1
Table 63.
INTERP1_ACCUM1
Register
Bits Name Description Type Reset
31:0 NONAME RW 0x00000000
INTERP1_BASE0 Register
Description
Read/write access to BASE0 register.
RP2040 Datasheet
2.3. Processor subsystem 60