Datasheet

Tx FIFO Buffer
FIFO Status Prior to
Transfer
FIFO Status on
Completion of Transfer
Rx FIFO Buffer
Location n
Location 2
Location 1
Location 0
Location n
Location 2
Location 1
Location 0
Write DR
NULL
NULL SHIFT LOGIC
Tx Data(1)
Tx Data(0)
Rx FIFO Empty
rxd
txd
NULL
NULL
NULL
NULL
Tx FIFO Empty
Read DR
Figure 125. FIFO
Status for Transmit
Only SPI and SSP
Transfers
For receive only transfers (transfer mode field (9:8) of the Control Register 0 = 10b), data transmitted from the DW_apb_ssi
to the external serial device is invalid, so a single dummy word is written into the transmit FIFO to begin the serial transfer.
The txd output from the DW_apb_ssi is held at a constant logic level for the duration of the serial transfer. Data received
from the external serial device into the DW_apb_ssi is pushed into the receive FIFO.
Figure 126 shows the FIFO levels prior to the beginning of a serial transfer and the FIFO levels on completion of the
transfer. In this example, two data words are received by the DW_apb_ssi from the external serial device in a continuous
transfer.
Tx FIFO Buffer
FIFO Status Prior to
Transfer
FIFO Status on
Completion of Transfer
Rx FIFO Buffer
Location n
Location 2
Location 1
Location 0
Location n
Location 2
Location 1
Location 0
Write DR
NULL
NULL SHIFT LOGIC
NULL
Dummy Word
Rx FIFO Empty
rxd
txd
NULL
Rx_Data(1)
Rx_Data(0)
NULL
Tx FIFO Empty
Read DR
Figure 126. FIFO
Status for Receive
Only SPI and SSP
Transfers
For eeprom_read transfers (transfer mode field [9:8] of the Control Register 0 = 11b), opcode and/or EEPROM address are
written into the transmit FIFO. During transmission of these control frames, received data is not captured by the
DW_apb_ssi master. After the control frames have been transmitted, receive data from the EEPROM is stored in the
receive FIFO.
Figure 127 shows the FIFO levels prior to the beginning of a serial transfer and the FIFO levels on completion of the
transfer. In this example, one opcode and an upper and lower address are transmitted to the EEPROM, and eight data
frames are read from the EEPROM and stored in the receive FIFO of the DW_apb_ssi master.
RP2040 Datasheet
4.11. SSI 604