Datasheet

You can write the SER register to enable the target slave for selection. If a slave is enabled here, the transfer
begins as soon as one valid data entry is present in the transmit FIFO. If no slaves are enabled prior to writing to
the DR register, the transfer does not begin until a slave is enabled.
3. Enable the DW_apb_ssi by writing 1 to the SSIENR register.
4. If the DW_apb_ssi master transmits data, write the control and data words into the transmit FIFO (write DR). If the
DW_apb_ssi master receives data, write the control word(s) into the transmit FIFO.
If no slaves were enabled in the SER register at this point, enable now to begin the transfer.
5. Poll the BUSY status to wait for completion of the transfer. The BUSY status cannot be polled immediately.
6. The transfer is stopped by the shift control logic when the transmit FIFO is empty. If the transfer mode is sequential
and the DW_apb_ssi master receives data, the transfer is stopped by the shift control logic when the specified
number of data frames is received. When the transfer is done, the BUSY status is reset to 0.
7. If the DW_apb_ssi master receives data, read the receive FIFO until it is empty.
8. Disable the DW_apb_ssi by writing 0 to SSIENR.
Figure 119 shows a typical software flow for starting a DW_apb_ssi master Microwire serial transfer. The diagram also
shows the hardware flow inside the serial-master component.
All bits in
data frame
transmitted?
Transmit
FIFO empty?
All frames
transferred?
Software Flow
DW_apb_ssi
IDLE
IDLE
END
Disable
DW_apb_ssi
Pop control frame
from Tx FIFO into
shifter
Enable
DW_apb_ssi
Transfer Bit
Transfer Bit
Pop data frame from
Tx FIFO into shifter
Receive Bit
Load Rx FIFO
Write control &
data to Tx FIFO
If master receives
data, user need only
write control frames
into the Tx FIFO.
Transfer begins
when first control
word is present in
the Transmit FIFO
and a slave is
enabled.
If the transmit FIFO
is requesting and all
data have not been
sent, then write data
into transmit FIFO.
If the receive FIFO is
requesting, then
read data from
receive FIFO.
Transfer in
progress
Interrupt Service
Routine
Read Rx
FIFO
Configure Master
by writing CTRLR0.
CTRLR1, BAUDR,
TXFTLR, RXFTLR,
MWCR, IMR, SER
Interrupt?
Yes
No
Yes
YesMWCR[1]=1 MWCR[1]=0
MWCR[0]=0
MWCR[0]=1
Yes
Yes
NoNo
No
Yes
Yes
MWCR[1]=1
No
All bits in
control frame
transmitted?
All bits in
data frame
received?
BUSY?
No
Figure 119.
DW_apb_ssi Master
Microwire Transfer
Flow
4.11.10. Partner Connection Interfaces
The DW_apb_ssi can connect to any serial-slave peripheral device using one of the interfaces discussed in the following
sections.
4.11.10.1. Motorola Serial Peripheral Interface (SPI)
With the SPI, the clock polarity (SCPOL) configuration parameter determines whether the inactive state of the serial clock
RP2040 Datasheet
4.11. SSI 601