Datasheet

Software Flow
DW_apb_ssi
IDLE
IDLE
END
Disable
DW_apb_ssi
Pop data from
Tx FIFO into shifter
Enable
DW_apb_ssi
Transfer Bit
Load Rx FIFO
Write data to
Tx FIFO
You may fill FIFO here:
Transfer begins when
first data word is
present in the transmit
FIFO and slave is
enabled.
If the transmit FIFO
is requesting and all
data have not been
sent, then write data
into transmit FIFO.
If the receive FIFO is
requesting, then
read data from
receive FIFO.
Transfer in
progress
Interrupt Service
Routine
Read Rx
FIFO
Configure Master by
writing CTRLR0. CTRLR1,
BAUDR, TXFTLR, RXFTLR,
IMR, SER, SPI_CTRLR0
(if Dual /Quad SPI)
Interrupt?
Yes
No
Yes
TMOD=01
TMOD=10
TMOD=00
TMOD=01
Yes
No No
Yes
Yes
TMOD=01
No
All bits in frame
transferred?
All frames
transferred
Transmit
FIFO empty?
BUSY?
No
Figure 118.
DW_apb_ssi Master
SPI/SSP Transfer Flow
4.11.9.1.4. Master Microwire Serial Transfers
Microwire serial transfers from the DW_apb_ssi serial master are controlled by the Microwire Control Register (MWCR).
The MWHS bit field enables and disables the Microwire handshaking interface. The MDD bit field controls the direction of
the data frame (the control frame is always transmitted by the master and received by the slave). The MWMOD bit field
defines whether the transfer is sequential or nonsequential.
All Microwire transfers are started by the DW_apb_ssi serial master when there is at least one control word in the transmit
FIFO and a slave is enabled. When the DW_apb_ssi master transmits the data frame (MDD = 1), the transfer is terminated
by the shift logic when the transmit FIFO is empty. When the DW_apb_ssi master receives the data frame (MDD = 1), the
termination of the transfer depends on the setting of the MWMOD bit field. If the transfer is nonsequential (MWMOD = 0),
it is terminated when the transmit FIFO is empty after shifting in the data frame from the slave. When the transfer is
sequential (MWMOD = 1), it is terminated by the shift logic when the number of data frames received is equal to the value
in the CTRLR1 register + 1.
When the handshaking interface on the DW_apb_ssi master is enabled (MWHS =1), the status of the target slave is polled
after transmission. Only when the slave reports a ready status does the DW_apb_ssi master complete the transfer and
clear its BUSY status. If the transfer is continuous, the next control/data frame is not sent until the slave device returns a
ready status.
A typical software flow for completing a Microwire serial transfer from the DW_apb_ssi serial master is outlined as
follows:
1. If the DW_apb_ssi is enabled, disable it by writing 0 to SSIENR.
2. Set up the DW_apb_ssi control registers for the transfer. These registers can be set in any order. Write CTRLR0 to set
transfer parameters.
◦
If the transfer is sequential and the DW_apb_ssi master receives data, write CTRLR1 with the number of frames
in the transfer minus 1; for instance, if you want to receive four data frames, write '3' into CTRLR1.
◦
Write BAUDR to set the baud rate for the transfer.
◦
Write TXFTLR and RXFTLR to set FIFO threshold levels.
◦
Write the IMR register to set up interrupt masks.
RP2040 Datasheet
4.11. SSI 600