Datasheet

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NOTE
EEPROM read mode is not supported when the DW_apb_ssi is configured to be in the SSP mode.
The receive FIFO threshold level (RXFTLR) can be used to give early indication that the receive FIFO is nearly full. When a
DMA is used for APB accesses, the receive data level (DMARDLR) can be used to early request (dma_rx_req) the DMA
Controller, indicating that the receive FIFO is nearly full.
A typical software flow for completing an SPI or SSP serial transfer from the DW_apb_ssi serial master is outlined as
follows:
1. If the DW_apb_ssi is enabled, disable it by writing 0 to the SSI Enable register (SSIENR).
2. Set up the DW_apb_ssi control registers for the transfer; these registers can be set in any order.
◦
Write Control Register 0 (CTRLR0). For SPI transfers, the serial clock polarity and serial clock phase parameters
must be set identical to target slave device.
◦
If the transfer mode is receive only, write CTRLR1 (Control Register 1) with the number of frames in the transfer
minus 1; for example, if you want to receive four data frames, if you want to receive four data frames, write '3'
into CTRLR1.
◦
Write the Baud Rate Select Register (BAUDR) to set the baud rate for the transfer.
◦
Write the Transmit and Receive FIFO Threshold Level registers (TXFTLR and RXFTLR, respectively) to set FIFO
threshold levels.
◦
Write the IMR register to set up interrupt masks.
◦
The Slave Enable Register (SER) register can be written here to enable the target slave for selection. If a slave is
enabled here, the transfer begins as soon as one valid data entry is present in the transmit FIFO. If no slaves are
enabled prior to writing to the Data Register (DR), the transfer does not begin until a slave is enabled.
3. Enable the DW_apb_ssi by writing 1 to the SSIENR register.
4. Write data for transmission to the target slave into the transmit FIFO (write DR). If no slaves were enabled in the SER
register at this point, enable it now to begin the transfer.
5. Poll the BUSY status to wait for completion of the transfer. The BUSY status cannot be polled immediately.
6. If a transmit FIFO empty interrupt request is made, write the transmit FIFO (write DR). If a receive FIFO full interrupt
request is made, read the receive FIFO (read DR).
7. The transfer is stopped by the shift control logic when the transmit FIFO is empty. If the transfer mode is receive only
(TMOD = 10b), the transfer is stopped by the shift control logic when the specified number of frames have been
received. When the transfer is done, the BUSY status is reset to 0.
8.
If the transfer mode is not transmit only (TMOD != 01b), read the receive FIFO until it is empty.
9. Disable the DW_apb_ssi by writing 0 to SSIENR.
Figure 118 shows a typical software flow for starting a DW_apb_ssi master SPI/SSP serial transfer. The diagram also
shows the hardware flow inside the serial-master component.
RP2040 Datasheet
4.11. SSI 599