Datasheet

DW_apb_ssi
Master 1
txd
ssi_oe_n
rxd
sclk_out
ss_n[0]
ss_n[1]
ss_in_n
Slave
Peripheral 1
DI
DO
SCLK
SS
Slave
Peripheral n
Should be driven to inactive level
(protocol-dependent) in single master
systems; may not need glue logic
DI
DO
SCLK
Glue Logic
SS
Figure 116.
DW_apb_ssi
Configured as Master
Device
The serial bit-rate clock, generated and controlled by the DW_apb_ssi, is driven out on the sclk_out line. When the
DW_apb_ssi is disabled (SSI_EN = 0), no serial transfers can occur and sclk_out is held in “inactive” state, as defined by the
serial protocol under which it operates.
Multiple master configuration is not supported.
4.11.9.1.1. RXD Sample Delay
When the DW_apb_ssi is configured as a master, additional logic can be included in the design in order to delay the default
sample time of the rxd signal. This additional logic can help to increase the maximum achievable frequency on the serial
bus.
Round trip routing delays on the sclk_out signal from the master and the rxd signal from the slave can mean that the
timing of the rxd signal—as seen by the master—has moved away from the normal sampling time. Figure 117 illustrates
this situation.
ssi_clk
sclk_out
txd_mst
rxd_mst
sclk_in
rxd_slv
txd_slv
dly=0
dly=5
dly=6
dly=7 baud-rate=4
MSB
MSB LSB
LSB
LSB
LSB
MSB
MSB
Figure 117. Effects of
Round-Trip Routing
Delays on sclk_out
Signal
The Slave uses the sclk_out signal from the master as a strobe in order to drive rxd signal data onto the serial bus.
Routing and sampling delays on the sclk_out signal by the slave device can mean that the rxd bit has not stabilized to the
correct value before the master samples the rxd signal. Figure 117 shows an example of how a routing delay on the rxd
signal can result in an incorrect rxd value at the default time when the master samples the port.
Without the RXD Sample Delay logic, the user would have to increase the baud-rate for the transfer in order to ensure that
RP2040 Datasheet
4.11. SSI 597