Datasheet

Table 603 provides description for different Transmit FIFO Threshold values.
Table 603. Transmit
FIFO Threshold (TFT)
Decode Values
TFT Value Description
0000_0000 ssi_txe_intr is asserted when zero data entries are present in transmit FIFO
0000_0001 ssi_txe_intr is asserted when one or less data entry is present in transmit FIFO
0000_0010 ssi_txe_intr is asserted when two or less data entries are present in transmit FIFO
… …
0000_1101 ssi_txe_intr is asserted when 13 or less data entries are present in transmit FIFO
0000_1110 ssi_txe_intr is asserted when 14 or less data entries are present in transmit FIFO
0000_1111 ssi_txe_intr is asserted when 15 or less data entries are present in transmit FIFO
Table 604 provides description for different Receive FIFO Threshold values.
Table 604. Receive
FIFO Threshold (TFT)
Decode Values
RFT Value Description
0000_0000 ssi_rxf_intr is asserted when one or more data entry is present in receive FIFO
0000_0001 ssi_rxf_intr is asserted when two or more data entries are present in receive FIFO
0000_0010 ssi_rxf_intr is asserted when three or more data entries are present in receive FIFO
… …
0000_1101 ssi_rxf_intr is asserted when 14 or more data entries are present in receive FIFO
0000_1110 ssi_rxf_intr is asserted when 15 or more data entries are present in receive FIFO
0000_1111 ssi_rxf_intr is asserted when 16 data entries are present in receive FIFO
4.11.6. 32-Bit Frame Size Support
The IP is configured to set the maximum programmable value in of data frame size to 32 bits. As a result the following
features exist:
•
dfs_32 (CTRLR0[20:16]) are valid, which contains the value of data frame size. The new register field holds the values
0 to 31. The dfs (CTRLR0[3:0]) is invalid and writing to this register has no effect.
•
The receive and transmit FIFO widths are 32 bits.
•
All 32 bits of the data register are valid.
4.11.7. SSI Interrupts
The DW_apb_ssi supports combined and individual interrupt requests, each of which can be masked. The combined
interrupt request is the ORed result of all other DW_apb_ssi interrupts after masking. Only the combined interrupt request
is routed to the Interrupt Controller. All DW_apb_ssi interrupts are level interrupts and are active high.
The DW_apb_ssi interrupts are described as follows:
Transmit FIFO Empty Interrupt (ssi_txe_intr)
Set when the transmit FIFO is equal to or below its threshold value and requires service to prevent an under-run. The
threshold value, set through a software-programmable register, determines the level of transmit FIFO entries at which
an interrupt is generated. This interrupt is cleared by hardware when data are written into the transmit FIFO buffer,
bringing it over the threshold level.
RP2040 Datasheet
4.11. SSI 594