Datasheet

sclk_out
ssi_clk
txd/rxd
MSB
capture2 capture3capture drive1 capture1 drive2 drive3
Figure 115. Maximum
sclk_out/ssi_clk Ratio.
The sclk_out line toggles only when an active transfer is in progress. At all other times it is held in an inactive state, as
defined by the serial protocol under which it operates.
The frequency of sclk_out can be derived from the following equation:
SCKDV is a bit field in the programmable register BAUDR, holding any even value in the range 0 to 65,534. If SCKDV is 0,
then sclk_out is disabled.
4.11.4.1. Frequency Ratio Summary
A summary of the frequency ratio restrictions between the bit-rate clock (sclk_out) and the DW_apb_ssi peripheral clock
(ssi_clk) are as follows:
•
4.11.5. Transmit and Receive FIFO Buffers
The FIFO buffers used by the DW_apb_ssi are internal D-type flip-flops that are 16 entries deep. The width of both transmit
and receive FIFO buffers is fixed at 32 bits, due to the serial specifications, which state that a serial transfer (data frame)
can be 4 to 16/32 bits in length. Data frames that are less than 32 bits must be right-justified when written into the
transmit FIFO buffer. The shift control logic automatically right-justifies receive data in the receive FIFO buffer.
Each data entry in the FIFO buffers contains a single data frame. It is impossible to store multiple data frames in a single
FIFO location; for example, you may not store two 8-bit data frames in a single FIFO location. If an 8-bit data frame is
required, the upper bits of the FIFO entry are ignored or unused when the serial shifter transmits the data.

NOTE
The transmit and receive FIFO buffers are cleared when the DW_apb_ssi is disabled (SSI_EN = 0) or when it is reset
(presetn).
The transmit FIFO is loaded by APB write commands to the DW_apb_ssi data register (DR). Data are popped (removed)
from the transmit FIFO by the shift control logic into the transmit shift register. The transmit FIFO generates a FIFO empty
interrupt request (ssi_txe_intr) when the number of entries in the FIFO is less than or equal to the FIFO threshold value.
The threshold value, set through the programmable register TXFTLR, determines the level of FIFO entries at which an
interrupt is generated. The threshold value allows you to provide early indication to the processor that the transmit FIFO is
nearly empty. A transmit FIFO overflow interrupt (ssi_txo_intr) is generated if you attempt to write data into an already full
transmit FIFO.
Data are popped from the receive FIFO by APB read commands to the DW_apb_ssi data register (DR). The receive FIFO is
loaded from the receive shift register by the shift control logic. The receive FIFO generates a FIFO-full interrupt request
(ssi_rxf_intr) when the number of entries in the FIFO is greater than or equal to the FIFO threshold value plus one. The
threshold value, set through programmable register RXFTLR, determines the level of FIFO entries at which an interrupt is
generated.
The threshold value allows you to provide early indication to the processor that the receive FIFO is nearly full. A receive
FIFO overrun interrupt (ssi_rxo_intr) is generated when the receive shift logic attempts to load data into a completely full
receive FIFO. However, this newly received data are lost. A receive FIFO underflow interrupt (ssi_rxu_intr) is generated if
you attempt to read from an empty receive FIFO. This alerts the processor that the read data are invalid.
RP2040 Datasheet
4.11. SSI 593