Datasheet

4.11.1. Overview
In order for the DW_apb_ssi to connect to a serial-master or serial-slave peripheral device, the peripheral must have a least
one of the following interfaces:
Motorola Serial Peripheral Interface (SPI)
A four-wire, full-duplex serial protocol from Motorola. There are four possible combinations for the serial clock phase
and polarity. The clock phase (SCPH) determines whether the serial transfer begins with the falling edge of the slave
select signal or the first edge of the serial clock. The slave select line is held high when the DW_apb_ssi is idle or
disabled.
Texas Instruments Serial Protocol (SSP)
A four-wire, full-duplex serial protocol. The slave select line used for SPI and Microwire protocols doubles as the
frame indicator for the SSP protocol.
National Semiconductor Microwire
A half-duplex serial protocol, which uses a control word transmitted from the serial master to the target serial slave.
You can program the FRF (frame format) bit field in the Control Register 0 (CTRLR0) to select which protocol is used.
The serial protocols supported by the DW_apb_ssi allow for serial slaves to be selected or addressed using either
hardware or software. When implemented in hardware, serial slaves are selected under the control of dedicated hardware
select lines. The number of select lines generated from the serial master is equal to the number of serial slaves present on
the bus. The serial-master device asserts the select line of the target serial slave before data transfer begins. This
architecture is illustrated in Figure 114.
When implemented in software, the input select line for all serial slave devices should originate from a single slave select
output on the serial master. In this mode it is assumed that the serial master has only a single slave select output. If there
are multiple serial masters in the system, the slave select output from all masters can be logically ANDed to generate a
single slave select input for all serial slave devices. The main program in the software domain controls selection of the
target slave device; this architecture is illustrated in Figure 114. Software would use the SSIENR register in all slaves in
order to control which slave is to respond to the serial transfer request from the master device.
The DW_apb_ssi does not enforce hardware or software control for serial-slave device selection. You can configure the
DW_apb_ssi for either implementation, illustrated in Figure 114.
Master
ss_0
ss_x
Slave
ss
Data Bus
ss = slave select line
Slave
ss
A
Master
ss
Slave
ss
Data Bus
Slave
ss
B
Figure 114.
Hardware/Software
Slave Selection.
4.11.2. Features
The DW_apb_ssi is a configurable and programmable component that is a full-duplex master serial interface. The host
processor accesses data, control, and status information on the DW_apb_ssi through the APB interface. The DW_apb_ssi
also interfaces with the DMA Controller for bulk data transfer.
The DW_apb_ssi is configured as a serial master. The DW_apb_ssi can connect to any serial-slave peripheral device using
one of the following interfaces:
RP2040 Datasheet
4.11. SSI 590