Datasheet

Bits Name Description Type Reset
23:20 Reserved. - - -
19:16 LEVEL The number of conversion results currently waiting in the
FIFO
RO 0x0
15:12 Reserved. - - -
11 OVER 1 if the FIFO has been overflowed. Write 1 to clear. WC 0x0
10 UNDER 1 if the FIFO has been underflowed. Write 1 to clear. WC 0x0
9 FULL RO 0x0
8 EMPTY RO 0x0
7:4 Reserved. - - -
3 DREQ_EN If 1: assert DMA requests when FIFO contains data RW 0x0
2 ERR If 1: conversion error bit appears in the FIFO alongside the
result
RW 0x0
1 SHIFT If 1: FIFO results are right-shifted to be one byte in size.
Enables DMA to byte buffers.
RW 0x0
0 EN If 1: write result to the FIFO after each conversion. RW 0x0
FIFO Register
Description
Conversion result FIFO
Table 597. FIFO
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15 ERR 1 if this particular sample experienced a conversion error.
Remains in the same location if the sample is shifted.
RF -
14:12 Reserved. - - -
11:0 VAL RF -
DIV Register
Description
Clock divider. If non-zero, CS_START_MANY will start conversions
at regular intervals rather than back-to-back.
The divider is reset when either of these fields are written.
Total period is 1 + INT + FRAC / 256
Table 598. DIV
Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:8 INT Integer part of clock divisor. RW 0x0000
7:0 FRAC Fractional part of clock divisor. First-order delta-sigma. RW 0x00
INTR Register
RP2040 Datasheet
4.10. ADC and Temperature Sensor 588