Datasheet

4.10.3.3. Sampling Multiple Inputs
CS.RROBIN allows the ADC to sample multiple inputs, in an interleaved fashion, while performing free-running sampling.
Each bit in RROBIN corresponds to one of the five possible values of CS.AINSEL. When the ADC completes a conversion,
<reg-adc-CS>>.AINSEL will automatically cycle to the next input whose corresponding bit is set in RROBIN.
The round-robin sampling feature is disabled by writing all-zeroes to CS.RROBIN.
For example, if AINSEL is initially 0, and RROBIN is set to 0x06 (bits 1 and 2 are set), the ADC will sample channels in the
following order:
1. Channel 0
2. Channel 1
3. Channel 2
4. Channel 1
5. Channel 2
6. Channel 1…

NOTE
The initial value of AINSEL does not need to correspond with a set bit in RROBIN.
4.10.3.4. Sample FIFO
The ADC samples can be read directly from the RESULT register, or stored in a local 4-entry FIFO and read out from FIFO.
FIFO operation is controlled by the FCS register.
If FCS.EN is set, the result of each ADC conversion is written to the FIFO. A software interrupt handler or the RP2040 DMA
can read this sample from the FIFO when notified by the ADC’s IRQ or DREQ signals. Alternatively, software can poll the
status bits in FCS to wait for each sample to become available.
If the FIFO is full when a conversion completes, the sticky error flag FCS.OVER is set. The current FIFO contents is not
changed by this event, but any conversion that completes whilst the FIFO is full will be lost.
There are two flags that control the data written to the FIFO by the ADC:
•
FCS.SHIFT will right-shift the FIFO data to eight bits in size (i.e. FIFO bits 7:0 are conversion result bits 11:4). This is
suitable for 8-bit DMA transfer to a byte buffer in memory, allowing deeper capture buffers, at the cost of some
precision.
•
FCS.ERR will set a flag at bit 12 of each FIFO entry, showing that a conversion error took place, i.e. the SAR failed to
converge TO DO: this needs a lot more explaintion as this isn’t typically adc behaviour

CAUTION
Conversion errors produce undefined results, and the corresponding sample should be discarded.
4.10.3.5. DMA
The ADC can request fetches from the DMA based on FIFO level, and enabled with FCS.DREQ_EN.
The DMA interface allows samples to be right-shifted to be one byte in size with FCS.SHIFT.
RP2040 Datasheet
4.10. ADC and Temperature Sensor 585