Datasheet

Table Of Contents
Four element receive sample FIFO
Interrupt generation
DMA interface
NOTE
When using an ADC input shared with a GPIO pin, the pin’s digital functions must be disabled by setting IE low and OD
high in the pin’s pad control register. See Section 2.18.6.3, “Pad Control - User Bank” for details. The maximum ADC
input voltage is determined by the digital IO supply voltage (IOVDD), not the ADC supply voltage (ADC_IOVDD). For
example, if IOVDD is powered at 1.8V, the voltage on the ADC inputs should not exceed 1.8V even if ADC_IOVDD is
powered at 3.3V. Voltages greater than IOVDD will result in leakage currents through the ESD protection diodes. See
Section 5.2.3, “Pin Specifications” for details.
Figure 112. ADC
Connection Diagram
4.10.2. ADC controller
A digital controller manages the details of operating the RP2040 ADC, and provides additional functionality:
One-shot or free-running capture mode
Sample FIFO with DMA interface
Pacing timer (16 integer bits, 8 fractional bits) for setting free-running sample rate
Round-robin sampling of multiple channels in free-running capture mode
Optional right-shift to 8 bits in free-running capture mode, so samples can be DMA’d to a byte buffer in system
memory
RP2040 Datasheet
4.10. ADC and Temperature Sensor 583