Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.4.1. Features
- 2.4.2. Functional Description
- 2.4.3. Programmer’s model
- 2.4.4. System control
- 2.4.5. NVIC
- 2.4.6. MPU
- 2.4.7. Debug
- 2.4.8. List of Registers
- 2.5. Memory
- 2.6. Boot Sequence
- 2.7. Bootrom
- 2.7.1. Bootrom Source
- 2.7.2. Processor Controlled Boot Sequence
- 2.7.3. Bootrom Contents
- 2.7.4. USB Mass Storage Interface
- 2.7.5. USB PICOBOOT Interface
- 2.8. Power Supplies
- 2.9. On-Chip Voltage Regulator
- 2.10. Power Control
- 2.11. Chip-Level Reset
- 2.12. Power-On State Machine
- 2.13. Subsystem Resets
- 2.14. Clocks
- 2.14.1. Overview
- 2.14.2. Clock sources
- 2.14.2.1. Ring Oscillator
- 2.14.2.1.1. Mitigating ROSC frequency variation due to process
- 2.14.2.1.2. Mitigating ROSC frequency variation due to voltage
- 2.14.2.1.3. Mitigating ROSC frequency variation due to temperature
- 2.14.2.1.4. Automatic mitigation of ROSC frequency variation due to PVT
- 2.14.2.1.5. Automatic overclocking using the ROSC
- 2.14.2.2. Crystal Oscillator
- 2.14.2.3. External Clocks
- 2.14.2.4. Relaxation Oscillators
- 2.14.2.5. PLLs
- 2.14.2.1. Ring Oscillator
- 2.14.3. Clock Generators
- 2.14.4. Frequency Counter
- 2.14.5. Resus
- 2.14.6. Programmer’s Model
- 2.14.7. List of registers
- 2.15. Crystal Oscillator (XOSC)
- 2.16. Ring Oscillator (ROSC)
- 2.17. PLL
- 2.18. GPIO
- 2.19. Sysinfo
- 2.20. Syscfg
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. DMA
- 4.3. UART
- 4.4. I2C
- 4.4.1. Features
- 4.4.2. IP Configuration
- 4.4.3. I2C Overview
- 4.4.4. I2C Terminology
- 4.4.5. I2C Behaviour
- 4.4.6. I2C Protocols
- 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.4.8. Multiple Master Arbitration
- 4.4.9. Clock Synchronization
- 4.4.10. Operation Modes
- 4.4.11. Spike Suppression
- 4.4.12. Fast Mode Plus Operation
- 4.4.13. Bus Clear Feature
- 4.4.14. IC_CLK Frequency Configuration
- 4.4.15. DMA Controller Interface
- 4.4.16. List of Registers
- 4.5. SPI
- 4.5.1. Overview
- 4.5.2. Functional Description
- 4.5.3. Operation
- 4.5.3.1. Interface reset
- 4.5.3.2. Configuring the SSP
- 4.5.3.3. Enable PrimeCell SSP operation
- 4.5.3.4. Clock ratios
- 4.5.3.5. Programming the SSPCR0 Control Register
- 4.5.3.6. Programming the SSPCR1 Control Register
- 4.5.3.7. Frame format
- 4.5.3.8. Texas Instruments synchronous serial frame format
- 4.5.3.9. Motorola SPI frame format
- 4.5.3.10. Motorola SPI Format with SPO=0, SPH=0
- 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1
- 4.5.3.12. Motorola SPI Format with SPO=1, SPH=0
- 4.5.3.13. Motorola SPI Format with SPO=1, SPH=1
- 4.5.3.14. National Semiconductor Microwire frame format
- 4.5.3.15. Examples of master and slave configurations
- 4.5.3.16. PrimeCell DMA interface
- 4.5.4. List of Registers
- 4.6. PWM
- 4.7. Timer
- 4.8. Watchdog
- 4.9. RTC
- 4.10. ADC and Temperature Sensor
- 4.11. SSI
- 4.11.1. Overview
- 4.11.2. Features
- 4.11.3. IP Modifications
- 4.11.4. Clock Ratios
- 4.11.5. Transmit and Receive FIFO Buffers
- 4.11.6. 32-Bit Frame Size Support
- 4.11.7. SSI Interrupts
- 4.11.8. Transfer Modes
- 4.11.9. Operation Modes
- 4.11.10. Partner Connection Interfaces
- 4.11.11. DMA Controller Interface
- 4.11.12. APB Interface
- 4.11.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
NOTE
While it is possible to change the CLKDIV_M1 on the fly, it is not recommended.
4.9.4.2. Setting up the clock
Write a near-future time to RTC setup registers. Write a 1 to the LOAD bit in the CTRL register, (this bit is self-clearing).
Then, at the appropriate time, enable the RTC using the ENABLE bit in the CTRL register. The RTC_ACTIVE bit in CTRL can
be read to confirm the RTC is running.
4.9.4.2.1. Adjusting the clock while running
It is possible to change the current time while the RTC is running. Write the desired values, then set the LOAD bit in the
CTRL register.
4.9.4.3. Reading the current time
TO DO: LIAM/ANDRAS: Sample code? Not all the time fields fit into one register read. To ensure a consistent value, we
need to read register RTC_0 first and RTC_1 after, in this order. Reading RTC_0 will read the live value and save a copy of
the data needed for RTC_1.
4.9.4.4. One-off alarm
TO DO: LIAM/ANDRAS: Sample code? Let’s say we want to set up an alarm for the 2026 solar eclipse
(https://moonblink.info/Eclipse/eclipse/2026_08_12). The total eclipse begins at 16:57:54 UT on 12 August, 2026. Write
the desired value into the setup_irq registers. No need to write the day of the week, it is redundant in this case. Enable
matching on all fields except for the day of the week, and enable global matching. Obviously, the RTC interrupt should be
enabled in the processor as well (outside the scope of this note)
Disable matching with an atomic write:
IRQ_SETUP_0.MATCH_ENA = 0
and wait until the status confirms that the matching became inactive
IRQ_SETUP_0.MATCH_ACTIVE = 0
Now it is safe to program the registers:
IRQ_SETUP_1.DOTW_ENA = 0
IRQ_SETUP_1.HOUR_ENA = 1
IRQ_SETUP_1.MIN_ENA = 1
IRQ_SETUP_1.SEC_ENA = 1
IRQ_SETUP_1.HOUR = 16
IRQ_SETUP_1.MIN = 57
IRQ_SETUP_1.SEC = 54
IRQ_SETUP_0.YEAR_ENA = 1
IRQ_SETUP_0.MONTH_ENA = 1
IRQ_SETUP_0.DAY_ENA = 1
IRQ_SETUP_0.YEAR = 2026
IRQ_SETUP_0.MONTH = 8
IRQ_SETUP_0.DAY = 12
Now, enable matching with an atomic write
IRQ_SETUP_0.MATCH_ENA = 1
and wait until the status confirms that the matching became active
RP2040 Datasheet
4.9. RTC 574