Datasheet

32 while(1);
33 }
4.8.6. List of registers
Table 573. List of
WATCHDOG registers
Offset Name Info
0x00 CTRL Watchdog control
The rst_wdsel register determines which subsystems are reset
when the watchdog is triggered.
The watchdog can be triggered in software.
0x04 LOAD Load the watchdog timer. The maximum setting is 0xffffff which
corresponds to 0xffffff / 2 ticks before triggering a watchdog
reset (see errata RP2040-E1).
0x08 REASON Logs the reason for the last reset. Both bits are zero for the case
of a hardware reset.
0x0c SCRATCH0 Scratch register. Information persists through soft reset of the
chip.
0x10 SCRATCH1 Scratch register. Information persists through soft reset of the
chip.
0x14 SCRATCH2 Scratch register. Information persists through soft reset of the
chip.
0x18 SCRATCH3 Scratch register. Information persists through soft reset of the
chip.
0x1c SCRATCH4 Scratch register. Information persists through soft reset of the
chip.
0x20 SCRATCH5 Scratch register. Information persists through soft reset of the
chip.
0x24 SCRATCH6 Scratch register. Information persists through soft reset of the
chip.
0x28 SCRATCH7 Scratch register. Information persists through soft reset of the
chip.
0x2c TICK Controls the tick generator
CTRL Register
Description
Watchdog control
The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.
The watchdog can be triggered in software.
Table 574. CTRL
Register
Bits Name Description Type Reset
31 TRIGGER Trigger a watchdog reset SC 0x0
30 ENABLE When not enabled the watchdog timer is paused RW 0x0
29:27 Reserved. - - -
RP2040 Datasheet
4.8. Watchdog 570