Datasheet

Table Of Contents
Table 44.
DIV_REMAINDER
Register
Bits Name Description Type Reset
31:0 NONAME RW 0x00000000
DIV_CSR Register
Description
Control and status register for divider.
Table 45. DIV_CSR
Register
Bits Name Description Type Reset
31:2 Reserved. - - -
1 DIRTY Changes to 1 when any register is written, and back to 0
when QUOTIENT is read.
Software can use this flag to make save/restore more
efficient (skip if not DIRTY).
If the flag is used in this way, it’s recommended to either
read QUOTIENT only,
or REMAINDER and then QUOTIENT, to prevent data loss
on context switch.
RO 0x0
0 READY Reads as 0 when a calculation is in progress, 1 otherwise.
Writing an operand (xDIVIDEND, xDIVISOR) will
immediately start a new calculation, no
matter if one is already in progress.
Writing to a result register will immediately terminate any
in-progress calculation
and set the READY and DIRTY flags.
RO 0x1
INTERP0_ACCUM0 Register
Description
Read/write access to accumulator 0
Table 46.
INTERP0_ACCUM0
Register
Bits Name Description Type Reset
31:0 NONAME RW 0x00000000
INTERP0_ACCUM1 Register
Description
Read/write access to accumulator 1
Table 47.
INTERP0_ACCUM1
Register
Bits Name Description Type Reset
31:0 NONAME RW 0x00000000
INTERP0_BASE0 Register
Description
Read/write access to BASE0 register.
RP2040 Datasheet
2.3. Processor subsystem 56