Datasheet

Table Of Contents
Bits Name Description Type Reset
1 CH1 RW 0x0
0 CH0 RW 0x0
INTS Register
Description
Interrupt status after masking & forcing
Table 554. INTS
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7 CH7 RO 0x0
6 CH6 RO 0x0
5 CH5 RO 0x0
4 CH4 RO 0x0
3 CH3 RO 0x0
2 CH2 RO 0x0
1 CH1 RO 0x0
0 CH0 RO 0x0
4.7. Timer
4.7.1. Overview
The timer peripheral on RP2040 supports the following features:
A single 64-bit counter, incrementing once per microsecond with the reference generated in the Watchdog (see
Section 4.8.2).
This counter can be read from a pair of latching registers, for race-free reads over a 32-bit bus.
Four alarms: match on the lower 32 bits of counter, IRQ on match.
Also note that each Cortex M0+ (see Cortex-M0+) is equipped with a 24-bit SysTick timer. This can be used to interrupt
itself.
The timer uses a one microsecond reference that is generated in the Watchdog (see Section 4.8.2) which comes from
clk_ref.
4.7.2. Counter
The timer has a 64-bit counter, but RP2040 only has a 32-bit data bus. This means that the TIME value is accessed through
a pair of registers. These are:
TIMEHW and TIMELW to write the time
TIMEHR and TIMELR to read the time
These pairs are used by accessing the lower register, L, followed by the higher register, H. In the read case, reading the L
register latches the value in the H register so that an accurate time can be read. Alternatively, TIMERAWH and TIMERAWL
RP2040 Datasheet
4.7. Timer 558