Datasheet

Description
Direct access to the PWM counter
Table 547. CH0_CTR,
CH1_CTR, …,
CH6_CTR, CH7_CTR
Registers
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 NONAME RW 0x0000
CH0_CC, CH1_CC, …, CH6_CC, CH7_CC Registers
Description
Counter compare values
Table 548. CH0_CC,
CH1_CC, …, CH6_CC,
CH7_CC Registers
Bits Name Description Type Reset
31:16 B RW 0x0000
15:0 A RW 0x0000
CH0_TOP, CH1_TOP, …, CH6_TOP, CH7_TOP Registers
Description
Counter wrap value
Table 549. CH0_TOP,
CH1_TOP, …,
CH6_TOP, CH7_TOP
Registers
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 NONAME RW 0xffff
EN Register
Description
This register aliases the CSR_EN bits for all channels.
Writing to this register allows multiple channels to be enabled
or disabled simultaneously, so they can run in perfect sync.
For each channel, there is only one physical EN register bit,
which can be accessed through here or CHx_CSR.
Table 550. EN Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7 CH7 RW 0x0
6 CH6 RW 0x0
5 CH5 RW 0x0
4 CH4 RW 0x0
3 CH3 RW 0x0
2 CH2 RW 0x0
1 CH1 RW 0x0
0 CH0 RW 0x0
INTR Register
RP2040 Datasheet
4.6. PWM 556