Datasheet

Table Of Contents
Offset Name Info
0xa4 INTR Raw Interrupts
0xa8 INTE Interrupt Enable
0xac INTF Interrupt Force
0xb0 INTS Interrupt status after masking & forcing
CH0_CSR, CH1_CSR, …, CH6_CSR, CH7_CSR Registers
Description
Control and status register
Table 545. CH0_CSR,
CH1_CSR, …,
CH6_CSR, CH7_CSR
Registers
Bits Name Description Type Reset
31:8 Reserved. - - -
7 PH_ADV Advance the phase of the counter by 1 count, while it is
running.
Self-clearing. Write a 1, and poll until low. Counter must be
running
at less than full speed (div_int + div_frac / 16 > 1)
SC 0x0
6 PH_RET Retard the phase of the counter by 1 count, while it is
running.
Self-clearing. Write a 1, and poll until low. Counter must be
running.
SC 0x0
5:4 DIVMODE 0x0 -> Free-running counting at rate dictated by fractional
divider
0x1 -> Fractional divider operation is gated by the PWM B
pin.
0x2 -> Counter advances with each rising edge of the PWM
B pin.
0x3 -> Counter advances with each falling edge of the
PWM B pin.
RW 0x0
3 B_INV Invert output B RW 0x0
2 A_INV Invert output A RW 0x0
1 PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge RW 0x0
0 EN Enable the PWM channel. RW 0x0
CH0_DIV, CH1_DIV, …, CH6_DIV, CH7_DIV Registers
Description
INT and FRAC form a fixed-point fractional number.
Counting rate is system clock frequency divided by this number.
Fractional division uses simple 1st-order sigma-delta.
Table 546. CH0_DIV,
CH1_DIV, …, CH6_DIV,
CH7_DIV Registers
Bits Name Description Type Reset
31:12 Reserved. - - -
11:4 INT RW 0x01
3:0 FRAC RW 0x0
CH0_CTR, CH1_CTR, …, CH6_CTR, CH7_CTR Registers
RP2040 Datasheet
4.6. PWM 555