Datasheet

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The TOP register
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Whether phase-correct mode is enabled (CSR_PH_CORRECT)
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The DIV register
The slice counts from 0 to TOP, and then either wraps, or begins counting backward, depending on the setting of
CSR_PH_CORRECT. The rate of counting is slowed by the clock divider, with a maximum speed of one count per cycle, and a
minimum speed of one count per cycles. The period in clock cycles can be calculated as:
The output frequency can then be determined based on the system clock frequency:
4.6.2.7. Interrupt Request (IRQ) and DMA Data Request (DREQ)
The PWM block has a single IRQ output. The interrupt status registers INTR, INTS and INTE allow software to control which
slices will assert this IRQ output, to check which slices are the cause of the IRQ’s assertion, and to clear and acknowledge
the interrupt.
A slice generates an interrupt request each time its counter wraps (or, if CSR_PH_CORRECT is enabled, each time the counter
returns to 0). This sets the flag corresponding to this slice in the raw interrupt status register, INTR. If this slice’s interrupt is
enabled in INTE, then this flag will cause the PWM block’s IRQ to be asserted, and the flag will also appear in the masked
interrupt status register INTS.
Flags are cleared by writing a mask back to INTR. This is demonstrated in the "LED fade" Pico SDK example.
This scheme allows multiple slices to generate interrupts concurrently, and a system interrupt handler to determine which
slices caused the most recent interruption, and handle appropriately. Normally this would mean reloading those slices' TOP
or CC registers, but the PWM block can also be used as a source of regular interrupt requests for non-PWM-related
purposes.
The same pulse which sets the interrupt flag in INTR is also available as a one-cycle data request to the RP2040 system
DMA. For each cycle the DMA sees a DREQ asserted, it will make one data transfer to its programmed location, in as
timely a manner as possible. In combination with the double-buffered behaviour of CC and TOP, this allows the DMA to
efficiently stream data to a PWM slice at a rate of one transfer per counter period. Alternatively, a PWM slice could serve
as a pacing timer for DMA transfers to some other memory-mapped hardware.
4.6.2.8. On-the-fly Phase Adjustment
For some applications it is necessary to control the phase relationship between two PWM outputs on different slices.
The global enable register EN contains an alias of the CSR_EN flag for each slice, and allows multiple slices to be started and
stopped simultaneously. If two slices with the same output frequency are started at the same time, they will run in perfect
lockstep, and have a fixed phase relationship, determined by the initial counter values.
The CSR_PH_ADV and CSR_PH_RET fields will advance or retard a slice’s output phase by one count, whilst it is running. They do
so by inserting or deleting pulses from the clock enable (the output of the clock divider), as shown in Figure 111.
RP2040 Datasheet
4.6. PWM 552