Datasheet

Count
enable
Fractional Clock
Divider (8.4)
Rising edge
Input
(pin B)
Event select
1
Falling edge
Phase
Advance
Phase
Retard
EN
Figure 110. PWM slice
event selection. The
counter advances
when its enable input
is high, and this
enable is generated in
two sequential stages.
First, any one of four
event types (always
on, pin B high, pin B
rise, pin B fall) can
generate enable
pulses for the
fractional clock
divider. The divider
can reduce the rate of
the enable pulses,
before passing them
on to the counter.
By default, each slice’s counter is free-running, and will count continuously whenever the slice is enabled. There are three
other options available:
•
Count continuously when a high level is detected on the B pin
•
Count once with each rising edge detected on the B pin
•
Count once with each falling edge detected on the B pin
These modes are selected by the DIVMODE field in each slice’s CSR. In free-running mode, the A and B pins are both outputs.
In any other mode, the B pin becomes an input, and controls the operation of the counter. CC_B is ignored when not in free-
running mode.
By allowing the slice to run for a fixed amount of time in level-sensitive or edge-sensitive mode, it’s possible to measure
the duty cycle or frequency of an input signal. Due to the type of edge-detect circuit used, the low period and high period
of the measured signal must both be strictly greater than the system clock period when taking frequency measurements.
The clock divider is still operational in level-sensitive and edge-sensitive mode. At maximum division (writing 0 to DIV_INT),
the counter will only advance once per 256 high input cycles in level-sensitive modes, or once per 256 edges in edge-
sensitive mode. This allows longer-running measurements to be taken, although the resolution is still just 16 bits.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pwm/measure_duty_cycle/measure_duty_cycle.c Lines 19 - 37
19 float measure_duty_cycle(uint gpio) {
20 // Only the PWM B pins can be used as inputs.
21 assert(pwm_gpio_to_channel(gpio) == PWM_CHAN_B);
22 pwm_inst_t slice = pwm_gpio_to_slice(gpio);
23
24 // Count once for every 100 cycles the PWM B input is high
25 pwm_config cfg = pwm_get_default_config();
26 pwm_config_divider_mode(&cfg, PWM_DIV_B_HIGH);
27 pwm_config_divider(&cfg, 100);
28 pwm_init(slice, &cfg, false);
29 gpio_set_function(gpio, GPIO_FUNC_PWM);
30
31 pwm_enable(slice, true);
32 sleep_ms(10);
33 pwm_enable(slice, false);
34 float counting_rate = clock_get_hz(clk_sys) / 100;
35 float max_possible_count = counting_rate * 0.01;
36 return pwm_get_counter(slice) / max_possible_count;
37 }
4.6.2.6. Configuring PWM Period
When free-running, the period of a PWM slice’s output (measured in system clock cycles) is controlled by three
parameters:
RP2040 Datasheet
4.6. PWM 551