Datasheet

Counter at top
0 1 2 3
IRQ
CC_A
0 1 2
CC_A latched
Figure 108. Each
counter wrap causes
the interrupt request
signal to assert. The
processor enters its
interrupt handler,
writes to its copy of
the CC register, and
clears the interrupt.
When the counter
wraps again, the
latched version of the
CC register is
instantaneously
updated with the most
recent value written by
software, and this
value controls the duty
cycle for the next
period. The IRQ is
reasserted so that
software can write
another fresh value to
its copy of the CC
register.
There is no limitation on what values can be written to CC or TOP, or when they are written. In normal PWM mode
(CSR_PH_CORRECT is 0) the latched copies are updated when the counter wraps to 0, which occurs once every TOP + 1 cycles.
In phase-correct mode (CSR_PH_CORRECT is 1), the latched copies are updated on the 0 to 0 count transition, i.e. the point
where the counter stops counting downward and begins to count upward again.
4.6.2.4. Clock Divider
Each slice has a fractional clock divider, configured by the DIV register. This is an 8 integer bit, 4 fractional bit clock divider,
which allows the count rate to be slowed by up to a factor of 256. The clock divider allows much lower output frequencies
to be achieved — approximately 7.5 Hz from a 125 MHz system clock. Lower frequencies than this will require a system
timer interrupt (Section 4.7)
It does this by generating an enable signal which gates the operation of the counter.
.0
DIV_FRAC
1
DIV_INT
.0
DIV_FRAC
Counter enable
3
DIV_INT
Counter enable
.5
DIV_FRAC
Counter enable
2
DIV_INT
Figure 109. The clock
divider generates an
enable signal. The
counter only counts on
cycles where this
signal is high. A clock
divisor of 1 causes the
enable to be asserted
on every cycle, so the
counter counts by one
on every system clock
cycle. Higher divisors
cause the count
enable to be asserted
less frequently.
Fractional division
achieves an average
fractional counting
rate by spacing some
enable pulses further
apart than others.
The fractional divider is a first-order delta-sigma type.
The clock divider also allows the effective count range to be extended, when using level-sensitive or edge-sensitive modes
to take duty cycle or frequency measurements.
4.6.2.5. Level-sensitive and Edge-sensitive Triggering
RP2040 Datasheet
4.6. PWM 550